Skyworks Solutions Inc. SI5335A-B04087-GMR

Overview

SI5335A-B04087-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis, delivering four independent non-integer-related frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL outputs in a 4×4 mm 24-QFN package. It serves as a single-chip replacement for multiple oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335A-B04087-GMR datasheet, SI5335A-B04087-GMR pinout, SI5335A-B04087-GMR application, or SI5335A-B04087-GMR equivalent, key selection considerations include its dual-loop-bandwidth PLL (1.6 MHz / 475 kHz), loss-of-signal alarm, five user-assignable control pins, and factory-programmable configuration via ClockBuilder Pro - all critical for PCIe jitter attenuation, Ethernet switch timing, and FPGA/processor clocking.

Technical Context

The SI5335A-B04087-GMR implements a single high-performance PLL with patented MultiSynth fractional-N dividers per output bank, enabling independent frequency synthesis without integer constraints. Its architecture supports both clock generator mode (full synthesis from crystal or reference input) and buffer mode (PLL bypass with <4 ns propagation delay).

Input flexibility includes 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references; outputs are independently configurable per bank for format (LVPECL/LVDS/CML/HCSL/CMOS/SSTL), voltage (1.5/1.8/2.5/3.3 V), and enable control - all managed via pin-selectable configurations and programmable control pins (P1–P6).

Key Specifications

Pinout & Package

SI5335A-B04087-GMR is housed in a thermally enhanced 24-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet Figure 2 (Top View) and Table 10 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5341-A01AGM and ICS8430I-01LG, the SI5335A-B04087-GMR uniquely balances web-customizable synthesis, PCIe Gen4 compliance, and 4-output flexibility in a cost-optimized 24-QFN package - making it the optimal choice for new mid-tier switch, adapter, and embedded compute designs requiring field-upgradable timing.

Availability

SI5335A-B04087-GMR is available at Aetrix Electronics and suitable for PCIe Gen4 endpoint timing, Ethernet switch synchronization, and FPGA clocking applications requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.

Supply support for SI5335A-B04087-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5335 family is designed as a highly configurable, any-frequency clock generator/buffer targeting high-speed serial interface timing in datacenter, telecom, and broadcast equipment - emphasizing jitter performance, configurability, and rapid customization.

FAQ

What is the primary function of the SI5335A-B04087-GMR in a PCIe Gen4 system?

The SI5335A-B04087-GMR serves as a compliant common clock source, generating four low-jitter 100 MHz reference clocks with ≤0.45 ps RMS jitter (measured per PCIe Gen4 spec) and integrated spread-spectrum control. Its dual-loop-bandwidth PLL and loss-of-signal alarm ensure robust timing integrity across root complexes and endpoints without external components.

Does the SI5335A-B04087-GMR support crystal input, and what frequencies are qualified?

Yes, the SI5335A-B04087-GMR supports on-chip 25 MHz and 27 MHz crystal oscillation with internal 18 pF load capacitance. Both frequencies are fully characterized per Tables 6 and 7 of the datasheet, including ESR limits (≤100 Ω for 25 MHz, ≤75 Ω for 27 MHz) and drive-level compliance (≤100 µW).

How many independent output voltage domains does the SI5335A-B04087-GMR support?

The SI5335A-B04087-GMR supports four independent output supply domains (VDDO0–VDDO3), each configurable from 1.4 V to 3.63 V. This enables simultaneous delivery of 1.8 V HCSL to a CPU, 2.5 V LVDS to an ASIC, 3.3 V CMOS to a legacy controller, and 1.5 V SSTL to memory interface - all from a single IC.

Can the SI5335A-B04087-GMR operate in clock buffer mode, and what is the propagation delay?

Yes, the SI5335A-B04087-GMR supports PLL-bypass (buffer) mode with typical input-to-output propagation delay of 2.5–4 ns. In this mode, it functions as a low-skew, level-translating fanout buffer with full output format and voltage configurability - ideal for retiming existing low-jitter references.

What control pin functions are available on the SI5335A-B04087-GMR, and how are they assigned?

The SI5335A-B04087-GMR provides five user-assignable control pins (P1, P2, P3, P5, P6) that can be configured as master/output-enable (OEB), spread-spectrum enable (SSENB), frequency-plan select (FS1/FS0), or device reset. Assignment is performed during ClockBuilder Pro configuration and locked in factory programming - no runtime I²C required.