Skyworks Solutions Inc. SI5335A-B04098-GMR

Overview

SI5335A-B04098-GMR from Skyworks Solutions is a quad-output, any-frequency clock generator with MultiSynth fractional synthesis, delivering four independent non-integer-related outputs up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and configurable LVPECL/LVDS/HCSL/CMOS/SSTL outputs - used in high-speed serial interface timing for Ethernet switches and PCIe root complexes.

For engineers reviewing the SI5335A-B04098-GMR datasheet, SI5335A-B04098-GMR pinout, SI5335A-B04098-GMR application, or SI5335A-B04098-GMR equivalent, key selection criteria include output format flexibility per bank, dual PLL loop bandwidth (1.6 MHz / 475 kHz), loss-of-signal alarm, spread spectrum control via P5/P6 pins, and factory-customizable configuration via ClockBuilder Pro.

Technical Context

The SI5335A-B04098-GMR integrates a single high-performance PLL with four independent MultiSynth fractional dividers, enabling simultaneous synthesis of unrelated frequencies without reference multiplication. Its architecture supports both clock generator mode (PLL active) and low-jitter buffer mode (PLL bypass), with input options including 25/27 MHz crystal, CMOS (10–200 MHz), or differential (10–350 MHz).

Each of the four output banks can be independently configured for differential (LVPECL/LVDS/CML/HCSL) or single-ended (CMOS/SSTL/HSTL) signaling, with per-driver VDDO selectable at 1.5/1.8/2.5/3.3 V. Control logic includes five user-assignable pins (P1–P3, P5, P6) supporting SSENB, FS[1:0], RESET, and master/output-specific OEB functions.

Key Specifications

Pinout & Package

SI5335A-B04098-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5335 layout: dual differential inputs (XA/CLKIN, XB/CLKINB) on Pins 1–2; four differential output pairs (CLK0A/B through CLK3A/B) across Pins 6–7, 9–10, 13–14, 18–19; LOS alarm on Pin 8; five multifunction control pins (P1–P3, P5, P6) on Pins 11, 12, 15, 21, 22; and dedicated VDD, VDDOx, and GND rails.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-B-GM, SI5335A-B04098-GMR delivers identical output flexibility at 40% lower core current and 25% smaller footprint, while ICS8430I-01T lacks synthesis capability entirely - making SI5335A-B04098-GMR the only option supporting custom frequency plans from a single crystal.

Availability

SI5335A-B04098-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, 10/25 GbE switch timing, and broadcast video synchronization requiring stable component supply, factory-programmed configuration, and long-term industrial temperature support.

Supply support for SI5335A-B04098-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line was designed to replace multiple discrete clock sources with a single programmable, low-jitter generator for high-speed serial interfaces - targeting PCIe, Ethernet, Fibre Channel, and telecom infrastructure applications.

FAQ

What is the maximum output frequency supported by SI5335A-B04098-GMR in LVPECL mode?

The SI5335A-B04098-GMR supports up to 350 MHz in LVPECL output mode, as specified in Table 4 of the datasheet. This applies when VDDO is set to 3.3 V and load conditions meet the 50 Ω differential termination requirement. Operation above 250 MHz requires careful attention to PCB routing and power supply decoupling to maintain jitter performance below 0.7 ps RMS.

Does SI5335A-B04098-GMR support PCIe Gen 4 Common Clock architecture?

Yes, SI5335A-B04098-GMR is compliant with PCIe Gen 4 Common Clock requirements, delivering <0.45 ps RMS jitter (10 kHz–50 MHz) when configured with 100 MHz HCSL outputs and 1.6 MHz PLL loop bandwidth. This meets the PCI-SIG Base Specification 4.0 rev. 0.5 jitter limit for Gen 4 common clock receivers.

Can SI5335A-B04098-GMR operate without an external crystal?

Yes, SI5335A-B04098-GMR can operate without an external crystal by accepting a single-ended CMOS or differential clock input (10–350 MHz) on Pins 1 and 2. The device also supports internal crystal oscillator circuitry for 25 MHz or 27 MHz fundamental-mode crystals, but crystal-less operation is fully functional in both PLL and buffer modes.

How many independent output voltage supplies does SI5335A-B04098-GMR support?

SI5335A-B04098-GMR supports four independent output voltage supplies: VDDO0, VDDO1, VDDO2, and VDDO3. Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling direct interfacing with mixed-voltage devices such as 1.8 V FPGAs, 2.5 V SerDes, and 3.3 V legacy controllers without external level translators.

What is the function of the LOS pin on SI5335A-B04098-GMR?

The LOS (Loss-of-Signal) pin on SI5335A-B04098-GMR is an open-drain output that asserts low within 2.6–5 µs when the input clock (on XA/XB or single-ended CLKIN) fails or drops below valid threshold levels. It releases within 0.01–1 µs after input recovery, providing fast fault detection for system watchdog or failover logic without requiring external monitoring circuitry.