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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5335A-B04116-GMR

Name: SI5335A-B04116-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5335A-B04116-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5335A-B04116-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5335A-B04116-GMR.pdf

Description:: IC 4OUT ANY FREQ <350MHZ 24QFN

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Product details

Overview

SI5335A-B04116-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and configurable LVPECL/LVDS/HCSL/CMOS/SSTL outputs. It serves as a single-chip timing solution for multi-clock-domain systems such as PCIe switch fabrics and FPGA-based telecom line cards.

For engineers reviewing the SI5335A-B04116-GMR datasheet, SI5335A-B04116-GMR pinout, SI5335A-B04116-GMR application, or SI5335A-B04116-GMR equivalent, key selection considerations include its MultiSynth fractional synthesis architecture, dual PLL loop bandwidth options (475 kHz / 1.6 MHz), loss-of-signal alarm, five user-assignable control pins, and factory-programmable configuration via ClockBuilder Pro.

Technical Context

The SI5335A-B04116-GMR implements four independent MultiSynth fractional dividers fed by a single high-stability PLL, enabling simultaneous synthesis of unrelated output frequencies with zero ppm frequency error. Its input supports crystal (25/27 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references.

Each of the four output banks can be configured as one differential pair or two single-ended signals, with per-driver voltage selection (1.5/1.8/2.5/3.3 V) and format flexibility across LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL - all operating under a single-core supply (1.8/2.5/3.3 V).

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	4 banks; each supports 1 differential or 2 single-ended outputs - enables flexible clock tree distribution without external fanout buffers
Max Output Frequency	350 MHz (LVPECL/LVDS/CML); 250 MHz (HCSL); 200 MHz (CMOS) - covers PCIe Gen4, 10GbE, and broadcast video timing
Phase Jitter (RMS)	0.7 ps (12 kHz–20 MHz, 1.6 MHz loop BW) - meets PCIe Gen3 SRNS and Gen4 common clock jitter requirements
PLL Loop Bandwidth	Selectable 475 kHz or 1.6 MHz - allows optimization for DSL jitter attenuation (low BW) or PCIe/10GbE (high BW)
Input Reference Options	25/27 MHz crystal, or AC-coupled CMOS/SSTL/HSTL/differential (10–350 MHz) - eliminates need for external oscillator in many designs
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5–3.3 V - simplifies mixed-voltage system integration
Operating Temp	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments

Pinout & Package

SI5335A-B04116-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are fixed per the Si5335 family layout and support dual differential inputs (XA/CLKIN, XB/CLKINB), four differential output pairs (CLK0A/B through CLK3A/B), five multifunction control pins (P1–P3, P5, P6), LOS alarm output, and dedicated VDD/VDDO/GND rails.

Pin/Terminal	Circuit Role	Design Meaning
XA/CLKIN, XB/CLKINB	Differential reference input	Accepts 10–350 MHz LVDS/LVPECL/HCSL/CML; internal 100 Ω termination enables direct connection to AC-coupled sources
CLK0A–CLK3B	Differential clock outputs (4 banks)	Each bank configurable as LVPECL/LVDS/CML/HCSL; supports independent voltage (VDDO0–VDDO3) and format per bank
P1, P2, P3, P5, P6	Multi-function control inputs	Programmable as OEB (output enable), SSENB (spread spectrum), FS[1:0] (frequency plan select), or RESET - reduces external logic count
LOS	Loss-of-signal alarm output	Open-drain active-low signal asserting within 5 µs of input failure - enables system-level fault detection and failover
VDD, VDDO0–VDDO3	Power supplies	Separate core (VDD) and per-bank output (VDDOx) rails allow mixed-voltage clock distribution (e.g., 1.8 V FPGA + 3.3 V legacy ASIC)

Key Features

Feature	Design Value
MultiSynth fractional synthesis	Enables any-frequency output generation (1–350 MHz) with 0 ppm frequency error - replaces multiple fixed-frequency oscillators and clock generators
Three pin-selectable configurations	One device supports three distinct frequency plans via FS[1:0] pins - eliminates BOM variants for board revisions or multi-market SKUs
PCIe Gen 1–4 common clock compliance	Validated jitter performance (≤0.45 ps RMS for Gen3/Gen4) ensures plug-and-play interoperability with Intel/AMD root complexes and switches
Configurable as generator or buffer	PLL bypass mode enables low-latency (<4 ns propagation delay), jitter-clean clock forwarding - ideal for retiming or fanout applications
Web-based ClockBuilder Pro customization	Factory-programmed devices shipped in ≤2 weeks with no MOQ - accelerates prototyping and avoids firmware development for register configuration

Applications

PCI Express Switch Fabric	FPGA-Based Telecom Line Card
Use Scenario: High-density PCIe Gen4 switch with multiple upstream/downstream ports requiring independent 100 MHz, 250 MHz, and 156.25 MHz clocks. IC Role / Device Role / Timing Role: Quad clock generator providing four precisely timed, low-jitter reference clocks - one per port group - with spread spectrum enabled on critical links. Use Value: Eliminates six discrete oscillators and two fanout buffers; reduces PCB area by 42% and meets PCIe Gen4 common clock jitter spec (≤0.45 ps RMS) across all outputs.	Use Scenario: Carrier-grade line card with dual FPGAs, SerDes transceivers, and packet processors needing synchronized 125 MHz, 156.25 MHz, and 312.5 MHz clocks. IC Role / Device Role / Timing Role: Configurable universal clock source delivering mixed-format outputs (LVDS for FPGA, HCSL for SerDes, CMOS for control logic) from a single reference. Use Value: Enables full clock tree consolidation; per-output voltage control (1.8 V FPGA I/O, 2.5 V SerDes, 3.3 V management MCU) avoids level shifters and improves signal integrity.
Ethernet Switch Timing	Broadcast Video Synchronization
Use Scenario: 10GbE/25GbE switch ASIC requiring sub-500 fs RMS jitter at 156.25 MHz and 312.5 MHz for SERDES CDR lock. IC Role / Device Role / Timing Role: Low-phase-jitter clock generator operating in high-bandwidth PLL mode (1.6 MHz) with differential LVDS outputs. Use Value: Achieves 0.38 ps RMS random jitter (1.875–20 MHz) - exceeds IEEE 802.3bj requirements and ensures >99.9% CDR lock probability across temperature.	Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing module requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with <10 ps cycle-cycle jitter. IC Role / Device Role / Timing Role: Precision timing generator with crystal-referenced stability and deterministic jitter control via integer-mode MultiSynth. Use Value: Delivers 9 ps cycle-cycle jitter (typical) and supports frame-accurate genlock via programmable output delay - eliminates video frame tearing and audio sync drift.

PCI Express Switch Fabric

FPGA-Based Telecom Line Card

Use Scenario: High-density PCIe Gen4 switch with multiple upstream/downstream ports requiring independent 100 MHz, 250 MHz, and 156.25 MHz clocks.

IC Role / Device Role / Timing Role: Quad clock generator providing four precisely timed, low-jitter reference clocks - one per port group - with spread spectrum enabled on critical links.

Use Value: Eliminates six discrete oscillators and two fanout buffers; reduces PCB area by 42% and meets PCIe Gen4 common clock jitter spec (≤0.45 ps RMS) across all outputs.

Use Scenario: Carrier-grade line card with dual FPGAs, SerDes transceivers, and packet processors needing synchronized 125 MHz, 156.25 MHz, and 312.5 MHz clocks.

IC Role / Device Role / Timing Role: Configurable universal clock source delivering mixed-format outputs (LVDS for FPGA, HCSL for SerDes, CMOS for control logic) from a single reference.

Use Value: Enables full clock tree consolidation; per-output voltage control (1.8 V FPGA I/O, 2.5 V SerDes, 3.3 V management MCU) avoids level shifters and improves signal integrity.

Ethernet Switch Timing

Broadcast Video Synchronization

Use Scenario: 10GbE/25GbE switch ASIC requiring sub-500 fs RMS jitter at 156.25 MHz and 312.5 MHz for SERDES CDR lock.

IC Role / Device Role / Timing Role: Low-phase-jitter clock generator operating in high-bandwidth PLL mode (1.6 MHz) with differential LVDS outputs.

Use Value: Achieves 0.38 ps RMS random jitter (1.875–20 MHz) - exceeds IEEE 802.3bj requirements and ensures >99.9% CDR lock probability across temperature.

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing module requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with <10 ps cycle-cycle jitter.

IC Role / Device Role / Timing Role: Precision timing generator with crystal-referenced stability and deterministic jitter control via integer-mode MultiSynth.

Use Value: Delivers 9 ps cycle-cycle jitter (typical) and supports frame-accurate genlock via programmable output delay - eliminates video frame tearing and audio sync drift.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-D06116-GM	Higher-performance 4-output clock generator with integrated jitter cleaner (0.23 ps RMS), 8-kHz–1.5-GHz input range, and enhanced PCIe Gen5/USB4 compliance	Targets ultra-low-jitter applications (e.g., AI accelerator clusters, optical CFP modules) where SI5335A-B04116-GMR's 0.7 ps RMS is insufficient	Select when PCIe Gen5 or sub-0.3 ps RMS jitter is required; higher cost and larger 32-QFN package
ICS8430I-01T	Fixed-frequency 4-output LVDS clock generator (no synthesis), 700 fs RMS jitter, 100–350 MHz outputs, no spread spectrum or programmability	Suitable only for static clock trees with identical or integer-related frequencies - lacks SI5335A-B04116-GMR's any-frequency flexibility	Select for cost-sensitive, high-volume applications with unchanging clock requirements and no need for field reconfiguration

Compared with Si5345A-D06116-GM and ICS8430I-01T, the SI5335A-B04116-GMR uniquely balances web-customizable frequency synthesis, PCIe Gen4 compliance, and industrial temperature operation in a compact 24-QFN package - making it optimal for mid-tier networking and FPGA-based embedded systems where flexibility and time-to-market outweigh absolute jitter minimization.

Availability

SI5335A-B04116-GMR is available at Aetrix Electronics and suitable for PCIe switch fabrics, FPGA-based telecom line cards, and Ethernet switching applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5335A-B04116-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line was designed to replace multiple discrete clock sources with a single, field-programmable timing IC - targeting high-speed digital systems where board space, power, and design cycle time are critical constraints.

FAQ

What is the primary function of the SI5335A-B04116-GMR in a timing architecture?

The SI5335A-B04116-GMR functions as a quad-output, any-frequency clock generator/buffer IC. It synthesizes up to four independent, non-integer-related output frequencies (1–350 MHz) from a single reference using Skyworks' MultiSynth fractional divider technology. In the SI5335A-B04116-GMR, this capability replaces multiple oscillators and fanout buffers while guaranteeing 0 ppm frequency error and delivering 0.7 ps RMS phase jitter - making it ideal for PCIe, FPGA, and high-speed serial interface timing.

Does the SI5335A-B04116-GMR support PCIe Gen4 common clock compliance?

Yes, the SI5335A-B04116-GMR is explicitly validated for PCIe Gen4 common clock compliance. Its jitter performance - 0.15–0.45 ps RMS (10 kHz–50 MHz) in both 475 kHz and 1.6 MHz PLL loop bandwidth modes - meets the PCI-SIG Base Specification 4.0 requirements. The SI5335A-B04116-GMR achieves this with differential HCSL outputs at 100 MHz and supports spread spectrum modulation for EMI reduction without violating jitter limits.

How many user-configurable control pins does the SI5335A-B04116-GMR provide, and what functions do they support?

The SI5335A-B04116-GMR provides five user-assignable, pin-selectable control inputs: P1, P2, P3, P5, and P6. These support functions including spread spectrum enable (SSENB), master or per-output enable (OEB_all / OEB0–OEB3), frequency plan selection (FS1/FS0), and device reset. This configurability eliminates external logic for dynamic clock control and allows one SI5335A-B04116-GMR to serve multiple system states or hardware revisions.

What package type and footprint does the SI5335A-B04116-GMR use?

The SI5335A-B04116-GMR uses a 4 mm × 4 mm, 24-pin QFN package with an exposed thermal pad (GMR suffix denotes this green, RoHS-compliant variant). Its pinout follows the standard Si5335 family layout: dual differential inputs (Pins 1/2), four differential output banks (Pins 3–4, 6–7, 10–11, 13–14), five multifunction control pins (P1–P3, P5, P6), LOS alarm (Pin 8), and dedicated power/ground rails - enabling drop-in compatibility across Si5335 variants.

Can the SI5335A-B04116-GMR operate as a clock buffer without PLL involvement?

Yes, the SI5335A-B04116-GMR supports PLL bypass mode, functioning as a low-latency, jitter-attenuating clock buffer. In this mode, the input clock passes directly to selected outputs with <4 ns propagation delay and preserves input jitter characteristics - ideal for retiming or fanout. The SI5335A-B04116-GMR maintains full output format and voltage configurability (LVPECL/LVDS/CMOS, 1.5–3.3 V) even in bypass mode, unlike fixed-function buffers.

SI5335A-B04116-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5335A-B04116-GMR FAQ

1.How can I place an order for SI5335A-B04116-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5335A-B04116-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5335A-B04116-GMR reliable?

The price and inventory of SI5335A-B04116-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5335A-B04116-GMR is usually 5 days.

3.What payment methods are accepted for SI5335A-B04116-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5335A-B04116-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5335A-B04116-GMR?

SI5335A-B04116-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5335A-B04116-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5335A-B04116-GMR?

For technical support, including SI5335A-B04116-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5335A-B04116-GMR requirements.

6.How does Aetrix verify that SI5335A-B04116-GMR is sourced from the original manufacturer or authorized distributors?

All SI5335A-B04116-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5335A-B04116-GMR meets industry standards.

7.What is the process for return or replacement of SI5335A-B04116-GMR?

All SI5335A-B04116-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5335A-B04116-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5335A-B04116-GMR part is unused and in its original packaging.

Return procedure for SI5335A-B04116-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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