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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5335A-B04130-GMR

Name: SI5335A-B04130-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5335A-B04130-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5335A-B04130-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5335A-B04130-GMR.pdf

Description:: IC 4OUT ANY FREQ <350MHZ 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5335A-B04130-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independently configurable output banks, synthesizing non-integer-related frequencies up to 350 MHz using MultiSynth fractional divider technology. It delivers 0 ppm frequency synthesis error, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It serves as a single-device replacement for multiple crystal oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335A-B04130-GMR datasheet, SI5335A-B04130-GMR pinout, SI5335A-B04130-GMR application, or SI5335A-B04130-GMR equivalent, key selection criteria include its dual PLL loop bandwidth options (475 kHz / 1.6 MHz), low 0.7 ps RMS phase jitter, flexible input support (25/27 MHz crystal, 10–350 MHz differential/single-ended), and per-output voltage configurability (1.5/1.8/2.5/3.3 V).

Technical Context

The SI5335A-B04130-GMR integrates a high-performance PLL with two selectable loop bandwidths (475 kHz for DSL jitter attenuation; 1.6 MHz for PCIe Gen 3/4) and four independent MultiSynth fractional dividers-each driving one differential pair or two single-ended outputs. Its architecture enables simultaneous synthesis of four unrelated frequencies without integer constraints.

It features five user-assignable multi-function pins (P1–P3, P5, P6) supporting spread-spectrum enable (SSENB), master/output-enable (OEB), frequency plan selection (FS1/FS0), and reset. Loss-of-signal (LOS) detection on CLKIN is implemented with 2.6–5 µs response time, and core supply current is 45 mA in clock generator mode and 12 mA in buffer mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	Four banks: each supports one LVPECL/LVDS/CML/HCSL differential pair or two CMOS/SSTL/HSTL single-ended outputs.
Max Output Frequency	350 MHz (LVPECL/LVDS/CML/SSTL/HSTL); 250 MHz (HCSL); 200 MHz (CMOS) - enables direct clocking of PCIe Gen 4 SerDes, 10GbE PHYs, and FPGA transceivers.
Phase Jitter (RMS)	0.7 ps (12 kHz–20 MHz, 1.6 MHz loop BW) - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements.
Input Flexibility	Supports 25/27 MHz crystal, or AC-coupled differential (10–350 MHz) / single-ended (10–200 MHz) reference clocks - eliminates need for external oscillator in many designs.
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per bank - allows mixed-voltage system interfacing without level shifters.
Operating Temp Range	–40 to +85 °C - qualified for industrial and telecom line card environments with no derating.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compact footprint compatible with high-density PCB layouts and automated assembly.

Pinout & Package

SI5335A-B04130-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is marked by dot; top marking includes "SI5335A" and date code. The package supports reflow soldering per JEDEC J-STD-020 and provides excellent thermal performance for continuous operation at full load.

Pin/Terminal	Circuit Role	Design Meaning
1, 2 (XA/CLKIN, XB/CLKINB)	Differential reference input	Accepts 10–350 MHz LVDS/LVPECL/HCSL/CML; internal 100 Ω termination option; supports crystal (25/27 MHz) via integrated oscillator.
3–4, 6–7, 10–11, 13–14 (CLK0A/B to CLK3A/B)	Differential clock outputs	Four independent banks; each pair configurable as LVPECL/LVDS/CML/HCSL; output voltage per bank set via VDDOx pins.
5, 8–9, 12, 15–16, 18–24 (VDD, VDDO0–VDDO3, GND, LOS, P1–P6, RSVD_GND)	Power, control & status	VDD = core supply (1.8/2.5/3.3 V); VDDOx = per-bank output supply (1.5–3.3 V); LOS = open-drain loss-of-signal alarm; P1–P6 = multi-function pins (OEB, FS, SSENB, RESET).

Key Features

Feature	Design Value
MultiSynth fractional synthesis	Enables 0 ppm frequency error across all four outputs - eliminates need for multiple crystals or trimming components in multi-clock systems.
Three pin-selectable configurations	Allows one device to serve three distinct system states (e.g., boot, normal, low-power) without firmware update or I²C communication.
PCIe Gen 1–4 & SRNS compliance	Validated jitter performance (≤0.45 ps RMS for Gen 3/4) ensures interoperability with Intel, AMD, and Broadcom SerDes without additional jitter cleaning.
Programmable output drivers	Each output bank supports format (LVDS/HCSL/CMOS/etc.) and voltage (1.5–3.3 V) selection - simplifies interface to mixed-voltage FPGAs, ASICs, and PHYs.
Loss-of-signal detection	Sub-5 µs LOS assertion enables fast failover or system reset in telecom and storage applications where clock integrity is safety-critical.
Web-based ClockBuilder Pro customization	Factory-programmed configuration delivered in ≤2 weeks with no MOQ - reduces design cycle time versus traditional mask-ROM clock ICs.

Applications

PCI Express Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized reference clocks to PCIe Gen 3/4 root complex and endpoint devices in server backplanes and accelerators. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) 100 MHz HCSL clocks compliant with PCIe common clock and SRNS specifications. Use Value: Eliminates four discrete oscillators and associated layout complexity while meeting strict PCIe jitter masks without external filtering.	Use Scenario: Generating precise 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch fabric and PHY interfaces. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing non-integer-related rates from a single 25 MHz crystal reference. Use Value: Enables single-reference, multi-rate clocking for mixed-speed Ethernet ports - reducing BOM count and improving inter-port skew.
FPGA & Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying core, I/O, transceiver, and DDR clock domains to Xilinx Versal or Intel Agilex FPGAs in compute-accelerated edge systems. IC Role / Device Role / Timing Role: Configurable universal buffer and level translator with per-output voltage (1.5–3.3 V) and format (LVDS/HCSL/CMOS) control. Use Value: Replaces multiple discrete buffers and level shifters - simplifying power domain partitioning and reducing board area.	Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) and ST 2081 (6G-SDI) reference clocks with sub-1 ps RMS jitter in broadcast video routers and recorders. IC Role / Device Role / Timing Role: Low-phase-jitter clock generator operating in 1.6 MHz loop bandwidth mode to suppress broadband noise affecting video signal integrity. Use Value: Meets SMPTE jitter limits (< 0.5 ps RMS) without external VCXO or jitter cleaners - lowering system cost and latency.

PCI Express Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized reference clocks to PCIe Gen 3/4 root complex and endpoint devices in server backplanes and accelerators.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) 100 MHz HCSL clocks compliant with PCIe common clock and SRNS specifications.

Use Value: Eliminates four discrete oscillators and associated layout complexity while meeting strict PCIe jitter masks without external filtering.

Use Scenario: Generating precise 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch fabric and PHY interfaces.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing non-integer-related rates from a single 25 MHz crystal reference.

Use Value: Enables single-reference, multi-rate clocking for mixed-speed Ethernet ports - reducing BOM count and improving inter-port skew.

FPGA & Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying core, I/O, transceiver, and DDR clock domains to Xilinx Versal or Intel Agilex FPGAs in compute-accelerated edge systems.

IC Role / Device Role / Timing Role: Configurable universal buffer and level translator with per-output voltage (1.5–3.3 V) and format (LVDS/HCSL/CMOS) control.

Use Value: Replaces multiple discrete buffers and level shifters - simplifying power domain partitioning and reducing board area.

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) and ST 2081 (6G-SDI) reference clocks with sub-1 ps RMS jitter in broadcast video routers and recorders.

IC Role / Device Role / Timing Role: Low-phase-jitter clock generator operating in 1.6 MHz loop bandwidth mode to suppress broadband noise affecting video signal integrity.

Use Value: Meets SMPTE jitter limits (< 0.5 ps RMS) without external VCXO or jitter cleaners - lowering system cost and latency.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-D06130-GM	Higher integration: 8 outputs, integrated jitter cleaner, ultra-low 0.23 ps RMS jitter; larger 32-QFN (5 × 5 mm) package.	Targeted at optical transport and 400G/800G Ethernet where sub-0.3 ps jitter and >4 outputs are mandatory.	Select Si5345A-D06130-GM only if ≥8 outputs, <0.3 ps jitter, or integrated jitter cleaning are required - otherwise SI5335A-B04130-GMR offers better cost and footprint efficiency.
ICS8430I-01T	Fixed-frequency quad LVDS buffer (no synthesis); 0.8 ps RMS jitter; 3.3 V only; no spread spectrum or programmable features.	Suitable only for simple fanout of existing clocks - lacks frequency flexibility, multi-voltage support, and PCIe compliance features.	Choose ICS8430I-01T only for legacy buffer-only use cases with fixed 100/125 MHz inputs - SI5335A-B04130-GMR adds synthesis, configurability, and compliance.

Compared with Si5345A-D06130-GM and ICS8430I-01T, SI5335A-B04130-GMR uniquely balances four-output synthesis flexibility, PCIe Gen 4 readiness, and compact 4 mm × 4 mm packaging - making it optimal for space-constrained, multi-protocol embedded systems requiring field-upgradable timing.

Availability

SI5335A-B04130-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server add-in cards, 10GbE switch line cards, and FPGA-based edge AI accelerators requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.

Supply support for SI5335A-B04130-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and mobile markets.

The Si5335 family was designed as a web-customizable, any-frequency clock generator/buffer platform targeting high-speed serial interface timing in datacenter, telecom, and broadcast equipment - emphasizing configurability, low jitter, and rapid time-to-market.

FAQ

What is the primary function of the SI5335A-B04130-GMR?

The SI5335A-B04130-GMR is a quad-output, web-customizable clock generator/buffer IC that synthesizes four independent, non-integer-related frequencies up to 350 MHz with 0 ppm frequency error. It replaces multiple oscillators and clock ICs in systems requiring PCIe Gen 1–4, Ethernet, FPGA, or broadcast video timing - and is factory-configured via Skyworks' ClockBuilder Pro tool.

Does the SI5335A-B04130-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335A-B04130-GMR is PCIe Gen 4 common clock compliant, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) in 1.6 MHz loop bandwidth mode with 100 MHz HCSL outputs. It meets the PCI-SIG Base Specification 4.0 rev. 0.5 jitter mask for Gen 4 without external cleanup circuitry.

Can the SI5335A-B04130-GMR operate with a 25 MHz crystal reference?

Yes, the SI5335A-B04130-GMR supports on-chip oscillation with standard 25 MHz or 27 MHz fundamental-mode crystals (18 pF load capacitance, ≤100 Ω ESR). No external oscillator or buffer is needed - the crystal connects directly to pins 1 and 2 (XA/XB), enabling simplified, low-cost clock tree design.

How many output formats does the SI5335A-B04130-GMR support per bank?

Each of the four output banks on the SI5335A-B04130-GMR supports LVPECL, LVDS, CML, HCSL, CMOS, SSTL, or HSTL - selectable per bank. Differential banks (CLK0A/B through CLK3A/B) can drive one differential pair; single-ended operation uses both pins of a bank as independent CMOS/SSTL outputs.

What is the significance of the "B04130" suffix in SI5335A-B04130-GMR?

The "B04130" suffix denotes a factory-programmed configuration generated via Skyworks' ClockBuilder Pro web utility. It specifies the exact frequency plan, output formats, voltage levels, control pin assignments (e.g., SSENB, FS0/FS1), and PLL settings - making SI5335A-B04130-GMR a fully functional, drop-in timing solution without runtime configuration.

SI5335A-B04130-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5335A-B04130-GMR FAQ

1.How can I place an order for SI5335A-B04130-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5335A-B04130-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5335A-B04130-GMR reliable?

The price and inventory of SI5335A-B04130-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5335A-B04130-GMR is usually 5 days.

3.What payment methods are accepted for SI5335A-B04130-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5335A-B04130-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5335A-B04130-GMR?

SI5335A-B04130-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5335A-B04130-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5335A-B04130-GMR?

For technical support, including SI5335A-B04130-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5335A-B04130-GMR requirements.

6.How does Aetrix verify that SI5335A-B04130-GMR is sourced from the original manufacturer or authorized distributors?

All SI5335A-B04130-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5335A-B04130-GMR meets industry standards.

7.What is the process for return or replacement of SI5335A-B04130-GMR?

All SI5335A-B04130-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5335A-B04130-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5335A-B04130-GMR part is unused and in its original packaging.

Return procedure for SI5335A-B04130-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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