Skyworks Solutions Inc. SI5335A-B04182-GMR

Overview

SI5335A-B04182-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis. It delivers four independent, non-integer-related output frequencies up to 350 MHz, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL/CML formats, achieves 0.7 ps RMS phase jitter, and operates across –40 to +85 °C in PCIe Gen 1–4 timing systems.

For engineers reviewing the SI5335A-B04182-GMR datasheet, SI5335A-B04182-GMR pinout, SI5335A-B04182-GMR application, or SI5335A-B04182-GMR equivalent, this page provides verified specifications, validated pin functions, PCIe-compliant jitter performance data, and confirmed alternative options for multi-frequency clocking in high-speed serial interfaces and FPGA/processor clock trees.

Technical Context

The SI5335A-B04182-GMR integrates a single PLL with two selectable loop bandwidths (1.6 MHz or 475 kHz) and four independent MultiSynth fractional dividers-each driving one output bank. Its architecture enables simultaneous synthesis of unrelated frequencies without reference multiplication, eliminating integer-N spurs and guaranteeing 0 ppm frequency error.

Input flexibility includes differential (LVPECL/LVDS/CML/HCSL, 10–350 MHz), single-ended CMOS (10–200 MHz), or 25/27 MHz crystal reference. Output drivers support per-bank voltage selection (1.5/1.8/2.5/3.3 V) and format reconfiguration, while five user-assignable control pins enable spread-spectrum control, frequency plan selection, and master/output-specific enables.

Key Specifications

Pinout & Package

SI5335A-B04182-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow the standard Si5335 top-view layout, with dedicated input (XA/CLKIN, XB/CLKINB), four output banks (CLK0A/B through CLK3A/B), supply rails (VDD, VDDO0–VDDO3), control pins (P1–P3, P5, P6), and status pin (LOS).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345A-D06182-GM and ICS8430I-01T, the SI5335A-B04182-GMR uniquely balances web-based customization, 0.7 ps RMS jitter, PCIe Gen 4 compliance, and quad-output flexibility-making it optimal for mid-tier networking and compute platforms where rapid iteration and mixed-voltage timing are required.

Availability

SI5335A-B04182-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, 10GbE switch clocking, and FPGA/ASIC clock tree applications requiring stable component supply, factory-programmed configuration, and industrial temperature range support.

Supply support for SI5335A-B04182-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line was designed to replace multiple fixed-frequency clock sources with a single, field-configurable, any-frequency generator-targeting high-speed serial interface timing in servers, switches, and programmable logic systems.

FAQ

What is the maximum output frequency supported by the SI5335A-B04182-GMR in LVPECL mode?

The SI5335A-B04182-GMR supports up to 350 MHz in LVPECL output mode, as specified in Table 4 of the official Skyworks datasheet Rev. 1.4. This applies to differential outputs with proper termination (100 Ω across differential pair) and VDDO ≥ 2.5 V. Operation above 250 MHz requires LVPECL or CML format; HCSL is limited to 250 MHz, and CMOS to 200 MHz.

Does the SI5335A-B04182-GMR support PCIe Gen 4 common clock compliance?

Yes, the SI5335A-B04182-GMR is explicitly PCIe Gen 4 common clock compliant per the PCI-SIG Base Specification 4.0 rev. 0.5. When configured with 100 MHz HCSL outputs and 1.6 MHz PLL bandwidth, it achieves ≤0.45 ps RMS jitter (Table 8), meeting the Gen 4 requirement. Spread spectrum is enabled by default for Gen 1–4 compatibility.

How many independent output voltage supplies does the SI5335A-B04182-GMR support?

The SI5335A-B04182-GMR supports five independent voltage domains: one core supply (VDD) and four output buffer supplies (VDDO0, VDDO1, VDDO2, VDDO3). Each VDDO rail can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling direct interface with mixed-voltage FPGAs, SerDes, and memory controllers without external level shifters.

Can the SI5335A-B04182-GMR operate without an external crystal?

Yes, the SI5335A-B04182-GMR can operate without an external crystal by using an external differential (LVDS/LVPECL/CML) or single-ended (CMOS/SSTL/HSTL) clock input between 10–350 MHz on pins XA/CLKIN and XB/CLKINB. The on-chip oscillator is only required when using a 25 or 27 MHz crystal; otherwise, the PLL locks directly to the applied reference signal.

What is the function of the LOS pin on the SI5335A-B04182-GMR?

The LOS (Loss-of-Signal) pin on the SI5335A-B04182-GMR is an open-drain output that asserts low within 5 µs of detecting CLKIN failure and releases within 1 µs after signal recovery. It provides real-time monitoring of reference clock integrity for system-level fault detection and failover control in telecom and industrial applications.