Skyworks Solutions Inc. SI5335A-B04403-GM

Overview

SI5335A-B04403-GM from Skyworks Solutions is a web-customizable, quad-output clock generator supporting four independent non-integer-related frequencies up to 350 MHz, with 0 ppm synthesis error via MultiSynth fractional divider technology. It operates in clock generator or buffer mode, features PCIe Gen 1–4 common clock compliance, and delivers 0.7 ps RMS phase jitter. It serves as a single-device replacement for multiple oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335A-B04403-GM datasheet, SI5335A-B04403-GM pinout, SI5335A-B04403-GM application, or SI5335A-B04403-GM equivalent, key selection considerations include its 4-output flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), dual PLL loop bandwidth options (1.6 MHz / 475 kHz), loss-of-signal detection, and pin-selectable frequency plans for multi-configuration system support.

Technical Context

The SI5335A-B04403-GM integrates a single PLL with four independent MultiSynth fractional dividers per output bank, enabling any-frequency synthesis without integer constraints. Its architecture supports both free-running clock generation and synchronous frequency translation, with configurable input sources including 25/27 MHz crystals, CMOS (10–200 MHz), or differential inputs (10–350 MHz).

Control logic includes five user-assignable pins (P1–P3, P5–P6) supporting spread spectrum enable (SSENB), master/output enables (OEB), frequency plan selection (FS[1:0]), and reset. The device implements loss-of-signal (LOS) monitoring on CLKIN/CLKINB and offers two selectable PLL loop bandwidths optimized for PCIe (1.6 MHz) or DSL (475 kHz) jitter attenuation.

Key Specifications

Pinout & Package

SI5335A-B04403-GM is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow the standard Si5335 top-view layout, with dedicated input (XA/CLKIN, XB/CLKINB), output (CLK0A–CLK3B), supply (VDD, VDDO0–VDDO3), control (P1–P3, P5–P6), and status (LOS) terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345A-D06403-GM, SI5335A-B04403-GM offers lower cost and smaller 4×4 mm footprint for 4-output needs, while retaining full PCIe Gen 4 compliance and web customization. Against ICS8430I-01LG, SI5335A-B04403-GM provides essential flexibility-any-frequency synthesis, multi-format outputs, and hardware-configurable frequency plans-without sacrificing jitter performance.

Availability

SI5335A-B04403-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switch fabric timing, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and factory-programmed configuration support.

Supply support for SI5335A-B04403-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications, automotive, and industrial markets.

The Si5335 product line was designed to replace multiple discrete clock sources with a single, field-programmable timing IC for high-speed serial interfaces-including PCIe, Ethernet, and broadcast video-where low jitter, format flexibility, and hardware configurability are critical.

FAQ

What is the primary function of the SI5335A-B04403-GM in a PCIe Gen 4 system?

The SI5335A-B04403-GM serves as a common clock generator delivering four synchronized, low-jitter reference clocks (e.g., 100 MHz HCSL) to root complex and endpoint devices. It meets PCIe Gen 4 common clock jitter limits (≤0.45 ps RMS) using its 1.6 MHz PLL loop bandwidth and MultiSynth synthesis engine - eliminating the need for four separate oscillators while ensuring reliable link training and stability in SI5335A-B04403-GM-based designs.

Does the SI5335A-B04403-GM support crystal input, and what frequencies are qualified?

Yes, the SI5335A-B04403-GM supports on-chip crystal oscillator operation with 25 MHz and 27 MHz fundamental-mode crystals. Both frequencies are fully qualified per Skyworks' crystal specifications: 25 MHz (18 pF load capacitance, ≤100 Ω ESR) and 27 MHz (18 pF load capacitance, ≤75 Ω ESR). The device automatically configures internal biasing and gain for either frequency, enabling robust, low-phase-noise reference generation without external components in SI5335A-B04403-GM applications.

How many independent output voltage supplies does the SI5335A-B04403-GM support, and why does this matter?

The SI5335A-B04403-GM supports five independent voltage supplies: one core supply (VDD) and four output buffer supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage FPGA I/O banks, processor peripherals, and SerDes PHYs without level shifters. For example, SI5335A-B04403-GM can drive 1.8 V LVDS memory clocks and 3.3 V CMOS control logic simultaneously - reducing component count and signal integrity risk in complex timing architectures.

Can the SI5335A-B04403-GM operate as a clock buffer, and what are the key benefits in that mode?

Yes, the SI5335A-B04403-GM supports PLL bypass (buffer) mode with 2.5–4 ns input-to-output propagation delay and only 12 mA core supply current. In this mode, it functions as a low-skew, multi-format fanout buffer - accepting a single reference (e.g., 100 MHz differential input) and distributing it across four independently formatted outputs (e.g., LVDS, HCSL, CMOS). This capability makes SI5335A-B04403-GM ideal for legacy system upgrades where existing clocks must be redistributed without adding jitter or requiring board redesign.

What hardware configuration options are available on the SI5335A-B04403-GM, and how are they implemented?

The SI5335A-B04403-GM provides three independent, pin-selectable device configurations using FS[1:0] control pins (P5, P6) and a master OEB pin (P1). These allow hardware-switched selection among pre-programmed frequency plans - for example, Plan A: 100/125/156.25/250 MHz; Plan B: 74.25/148.5/297/594 MHz; Plan C: 27/54/108/216 MHz. Configuration is set at power-up and requires no I²C communication, making SI5335A-B04403-GM suitable for secure, firmware-free timing in aerospace and industrial control systems.