Skyworks Solutions Inc. SI5335A-B04403-GMR

Overview

SI5335A-B04403-GMR from Skyworks Solutions is a quad-output, any-frequency clock generator with MultiSynth fractional synthesis, delivering four independent outputs up to 350 MHz (LVPECL/LVDS/CML), 250 MHz (HCSL), or 200 MHz (CMOS), 0 ppm frequency error, and 0.7 ps RMS phase jitter. It supports PCIe Gen 1–4 common clock and SRNS compliance, and operates across –40 to +85 °C in a 4 × 4 mm 24-QFN package for high-density timing applications.

For engineers reviewing the SI5335A-B04403-GMR datasheet, SI5335A-B04403-GMR pinout, SI5335A-B04403-GMR application, or SI5335A-B04403-GMR equivalent, key selection criteria include differential output format support (LVPECL/LVDS/HCSL/CML/CMOS), dual PLL loop bandwidth options (475 kHz / 1.6 MHz), loss-of-signal detection, pin-selectable frequency plans, and PCIe jitter compliance at Gen 3/4.

Technical Context

The SI5335A-B04403-GMR integrates four independent MultiSynth fractional dividers fed by a single PLL, enabling simultaneous synthesis of non-integer-related frequencies without inter-channel coupling. Each output bank supports configurable drive strength, voltage (1.5/1.8/2.5/3.3 V), and format-allowing mixed LVDS, HCSL, and CMOS outputs on a single device.

It accepts flexible references: 25/27 MHz crystal, or AC-coupled differential (10–350 MHz) or single-ended (10–200 MHz) inputs. Two selectable PLL loop bandwidths (475 kHz or 1.6 MHz) optimize jitter attenuation for DSL or PCIe applications, while five programmable control pins (P1–P6) enable spread spectrum control, master/output enables, and frequency plan selection.

Key Specifications

Pinout & Package

SI5335A-B04403-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are fully programmable via configuration bits and pin strapping; default assignments align with Si5335 family architecture.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5332A-D06403-GM and ICS843002AGI-01LFT, the SI5335A-B04403-GMR uniquely balances field-programmable frequency agility, PCIe Gen 4 compliance, and compact 24-QFN packaging - making it optimal for mid-complexity systems requiring design reuse across multiple platforms via pin-selectable configurations.

Availability

SI5335A-B04403-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server boards, 10/25 GbE switch designs, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5335A-B04403-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si5335 product line delivers web-customizable, any-frequency clock generators targeting high-performance computing, networking, and telecom infrastructure where jitter, flexibility, and small footprint are critical.

FAQ

What is the primary function of the SI5335A-B04403-GMR in a PCIe Gen 4 system?

The SI5335A-B04403-GMR serves as a compliant common clock generator, synthesizing precise 100 MHz reference clocks for root complex and endpoint devices. It meets PCIe Gen 4 jitter requirements (≤0.45 ps RMS) using its 1.6 MHz PLL loop bandwidth and HCSL outputs, and supports spread spectrum to reduce EMI. Its pin-selectable frequency plans allow one SI5335A-B04403-GMR to serve multiple PCIe configurations without firmware changes.

Does the SI5335A-B04403-GMR support both differential and single-ended output formats simultaneously?

Yes, the SI5335A-B04403-GMR supports mixed output formats: each of its four banks can be independently configured as LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL. For example, CLK0A/B may drive an FPGA with LVDS, while CLK2A drives a microcontroller with CMOS - all from the same SI5335A-B04403-GMR device, with per-bank VDDO voltage selection enabling interoperability.

How is loss-of-signal (LOS) detection implemented on the SI5335A-B04403-GMR?

The SI5335A-B04403-GMR monitors the XA/CLKIN and XB/CLKINB differential input continuously. Upon loss of valid clock signal, the open-drain LOS pin (Pin 8) asserts low within 5 µs and holds until signal recovery, which releases LOS within 1 µs. This fast response enables rapid system failover or diagnostic logging. The feature operates in both PLL and buffer modes and is unaffected by output configuration.

Can the SI5335A-B04403-GMR operate without an external crystal?

Yes, the SI5335A-B04403-GMR supports external AC-coupled clock inputs (10–350 MHz differential or 10–200 MHz single-ended) in place of a crystal. When using a crystal, only 25 MHz or 27 MHz types are supported, with internal 18 pF load capacitance and ≤100 Ω ESR. Crystal-less operation simplifies BOM and layout but requires a clean, low-jitter external reference to maintain the SI5335A-B04403-GMR's 0.7 ps RMS jitter performance.

What are the power supply requirements for the SI5335A-B04403-GMR core and outputs?

The SI5335A-B04403-GMR requires a single core supply (VDD) at 1.8 V, 2.5 V, or 3.3 V (±10%), and four independent output buffer supplies (VDDO0–VDDO3) each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. Core current is 45 mA in clock generator mode and 12 mA in buffer mode. Output currents vary by format and frequency - e.g., 30 mA per LVPECL output at 350 MHz - necessitating proper decoupling per supply rail.