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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5335A-B04671-GM

Name: SI5335A-B04671-GM
Brand: Skyworks Solutions Inc.
SKU: SI5335A-B04671-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5335A-B04671-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5335A-B04671-GM.pdf

Description:: IC 4OUT ANY FREQ <350MHZ 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5335A-B04671-GM from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with four independently synthesized non-integer-related frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL outputs in a 4×4 mm 24-QFN package. It serves as a multi-frequency timing source in high-speed serial interface systems.

For engineers reviewing the SI5335A-B04671-GM datasheet, SI5335A-B04671-GM pinout, SI5335A-B04671-GM application, or SI5335A-B04671-GM equivalent, key selection considerations include its MultiSynth fractional synthesis architecture, dual PLL loop bandwidth options (475 kHz / 1.6 MHz), loss-of-signal alarm, five user-assignable control pins, and factory-configurable pin-selectable frequency plans.

Technical Context

The SI5335A-B04671-GM implements Skyworks' patented MultiSynth fractional divider technology across four independent synthesis paths, enabling zero-ppm frequency error for any output frequency within 1–350 MHz (differential) or 1–200 MHz (CMOS). Its dual-loop-bandwidth PLL supports jitter attenuation in PCIe and DSL applications.

Input flexibility includes external crystal (25/27 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references. Output drivers are independently configurable per bank for voltage (1.5/1.8/2.5/3.3 V), format, and enable control, with up to four differential or eight single-ended outputs.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four banks: each supports one differential pair or two single-ended outputs - enables flexible clock tree distribution without external fanout buffers.
Max output frequency	350 MHz (LVPECL/LVDS/CML); 250 MHz (HCSL); 200 MHz (CMOS) - covers PCIe Gen4 reference (100 MHz), 10GbE (156.25 MHz), and broadcast video (270 MHz) requirements.
Phase jitter (RMS)	0.7 ps (12 kHz–20 MHz, 1.6 MHz loop BW) - meets PCIe Gen3 SRNS (≤0.32 ps) and Gen4 (≤0.45 ps) RMS jitter specs when configured per reference design.
PLL loop bandwidth	Selectable 475 kHz or 1.6 MHz - low BW optimizes DSL jitter attenuation; high BW targets PCIe Gen1–4 common clock compliance.
Supply voltage	VDD core: 1.8/2.5/3.3 V ±10%; VDDO per bank: 1.4–3.63 V - supports mixed-voltage system integration with independent I/O voltage control.
Operating temperature	–40 °C to +85 °C - qualified for industrial and telecom line card environments without derating.
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch - compact footprint compatible with high-density FPGA/ASIC timing layouts.

Pinout & Package

SI5335A-B04671-GM uses a 24-lead QFN package (4 mm × 4 mm) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
XA/CLKIN, XB/CLKINB (Pins 1, 2)	Differential input clock or crystal connection	Accepts 10–350 MHz differential reference or 25/27 MHz crystal; internal 18 pF load capacitance eliminates external caps for crystal mode.
CLK0A/CLK0B to CLK3A/CLK3B (Pins 3–4, 6–7, 10–11, 13–14)	Differential clock outputs (4 banks)	Each bank configurable for LVPECL/LVDS/HCSL/CML; supports independent voltage (VDDO0–VDDO3) and format per bank.
VDDO0–VDDO3 (Pins 5, 8, 9, 12)	Output buffer supply rails	Independent 1.4–3.63 V supplies per output bank - enables mixed-interface clocking (e.g., 1.8 V HCSL + 3.3 V CMOS on same device).
VDD (Pins 15, 16, 21, 22)	Core logic supply	Single 1.8/2.5/3.3 V supply powers PLL, MultiSynth dividers, and control logic; PSRR optimized for noise immunity.
P1–P3, P5–P6 (Pins 17–19, 23–24)	User-assignable control inputs	Configurable as SSENB (spread spectrum), RESET, OEB (output enable), or FS[1:0] (frequency plan select) - reduces external GPIO count.
LOS (Pin 20)	Loss-of-signal alarm output	Open-drain active-low signal asserts within 5 µs of input clock failure - enables system-level fault detection and failover.

Key Features

Feature	Design Value
MultiSynth fractional synthesis	Zero-ppm frequency error across all four outputs - eliminates need for multiple crystals or fixed-ratio PLLs in multi-clock systems.
Three pin-selectable configurations	One device replaces three discrete clock generators via FS[1:0] pins - simplifies BOM and enables field-upgradable timing schemes.
PCIe Gen 1–4 common clock compliance	Validated total jitter ≤33.6 ps pk-pk (Gen1 w/SS) and RMS jitter ≤0.45 ps (Gen3/Gen4) - meets spec without external jitter cleaners.
Flexible output driver control	Per-bank voltage (1.5/1.8/2.5/3.3 V), format (LVPECL/LVDS/HCSL/CMOS/SSTL), and enable - supports heterogeneous SoC/FPGA interfaces from one IC.
Low-power operation	45 mA core current (generator mode); 12 mA (buffer mode) - reduces thermal load in space-constrained telecom and networking modules.

Applications

PCI Express Gen 4 Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to CPU, GPU, and NVMe controllers in a Gen4 server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, integer-related 100 MHz clocks with PCIe Gen4 common clock compliance. Use Value: Eliminates four discrete oscillators; achieves 0.45 ps RMS jitter (meets Gen4 spec) using internal 1.6 MHz PLL bandwidth and HCSL outputs.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and switch fabric in a modular Ethernet switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing non-integer-related rates from a single 25 MHz crystal reference. Use Value: Replaces three separate clock ICs; supports mixed-rate PHY interfaces while maintaining <1 ps RMS jitter via MultiSynth fractional synthesis.
Broadcast Video Synchronization	DSLAM Jitter Attenuation
Use Scenario: Delivering SMPTE ST 2082 (270 MHz) and ST 2081 (540 MHz) reference clocks to video encoder/decoder ASICs in a 4K/8K production switcher. IC Role / Device Role / Timing Role: High-frequency clock generator with 350 MHz LVPECL outputs and ultra-low 0.7 ps RMS phase jitter. Use Value: Meets SMPTE jitter mask requirements; avoids external jitter cleaners by leveraging internal 1.6 MHz PLL bandwidth and differential signaling.	Use Scenario: Cleaning and regenerating 70.656 MHz line clock in a DSLAM line card with stringent 2.2 ps RMS (10 Hz–30 MHz) jitter limit. IC Role / Device Role / Timing Role: Jitter-attenuating clock buffer using 475 kHz PLL loop bandwidth and low-noise MultiSynth feedback path. Use Value: Reduces input jitter by >10×; achieves 2.2 ps RMS (RJDSL3) - satisfies ITU-T G.992.1 Annex A jitter compliance.

PCI Express Gen 4 Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to CPU, GPU, and NVMe controllers in a Gen4 server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, integer-related 100 MHz clocks with PCIe Gen4 common clock compliance.

Use Value: Eliminates four discrete oscillators; achieves 0.45 ps RMS jitter (meets Gen4 spec) using internal 1.6 MHz PLL bandwidth and HCSL outputs.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and switch fabric in a modular Ethernet switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing non-integer-related rates from a single 25 MHz crystal reference.

Use Value: Replaces three separate clock ICs; supports mixed-rate PHY interfaces while maintaining <1 ps RMS jitter via MultiSynth fractional synthesis.

Broadcast Video Synchronization

DSLAM Jitter Attenuation

Use Scenario: Delivering SMPTE ST 2082 (270 MHz) and ST 2081 (540 MHz) reference clocks to video encoder/decoder ASICs in a 4K/8K production switcher.

IC Role / Device Role / Timing Role: High-frequency clock generator with 350 MHz LVPECL outputs and ultra-low 0.7 ps RMS phase jitter.

Use Value: Meets SMPTE jitter mask requirements; avoids external jitter cleaners by leveraging internal 1.6 MHz PLL bandwidth and differential signaling.

Use Scenario: Cleaning and regenerating 70.656 MHz line clock in a DSLAM line card with stringent 2.2 ps RMS (10 Hz–30 MHz) jitter limit.

IC Role / Device Role / Timing Role: Jitter-attenuating clock buffer using 475 kHz PLL loop bandwidth and low-noise MultiSynth feedback path.

Use Value: Reduces input jitter by >10×; achieves 2.2 ps RMS (RJDSL3) - satisfies ITU-T G.992.1 Annex A jitter compliance.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5341-A02579-GM	8-output, higher integration (integrated crystal option), lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at high-end data converters and radar; requires ClockBuilder Pro v2.x configuration	Choose for JESD204B systems or when >4 outputs or sub-0.4 ps jitter required; not pin-compatible.
ICS8430I-01LG	4-output, fixed-ratio PLL (no fractional synthesis), 1.2 ps RMS jitter, no spread spectrum, 3.3 V only	Limited to integer-related frequencies; lacks LOS alarm and programmable control pins	Choose for cost-sensitive, fixed-frequency applications where MultiSynth flexibility is unnecessary.

Compared with Si5341-A02579-GM and ICS8430I-01LG, SI5335A-B04671-GM uniquely balances web-customizable any-frequency synthesis, PCIe Gen4 compliance, and 24-QFN compactness - making it optimal for mid-tier networking and compute platforms requiring field-reconfigurable timing without over-specification.

Availability

SI5335A-B04671-GM is available at Aetrix Electronics and suitable for PCIe Gen4 server boards, Ethernet switching fabric, broadcast video equipment, and DSLAM line cards requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.

Supply support for SI5335A-B04671-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5335 family is designed as a highly configurable, web-customizable clock generator/buffer platform targeting high-speed serial interface timing in networking, computing, and communications equipment - emphasizing flexibility, low jitter, and rapid time-to-market via ClockBuilder Pro.

FAQ

What is the primary function of the SI5335A-B04671-GM?

The SI5335A-B04671-GM is a quad-output, web-customizable clock generator/buffer IC that synthesizes up to four independent, non-integer-related frequencies from a single reference. It delivers low-jitter clock signals (0.7 ps RMS) for PCIe Gen1–4, Ethernet, broadcast video, and telecom applications using Skyworks' MultiSynth fractional divider technology.

Does the SI5335A-B04671-GM support spread spectrum clocking?

Yes, the SI5335A-B04671-GM supports spread spectrum clocking via the SSENB control pin. It provides –0.45% to –0.5% down-spread modulation at 31.5 kHz (PCI-compliant default), reducing EMI in high-density PCB layouts without impacting timing integrity.

How many output formats does the SI5335A-B04671-GM support per bank?

The SI5335A-B04671-GM supports LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL output formats per bank. Each of the four output banks can be independently configured for format, voltage (1.5/1.8/2.5/3.3 V), and enable state - enabling heterogeneous interface support from a single device.

What reference inputs are compatible with the SI5335A-B04671-GM?

The SI5335A-B04671-GM accepts 25 MHz or 27 MHz crystals directly (internal 18 pF load), or AC-coupled CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) clock inputs. Input impedance is 10 kΩ with 3.5 pF capacitance, and slew rate requirements are specified for optimal jitter performance.

Is the SI5335A-B04671-GM pin-compatible with other Si5335 variants?

Yes, all Si5335 variants including SI5335A-B04671-GM share identical 24-QFN packaging and pinout. Configuration differences (e.g., factory-programmed frequency plans, output formats, or control pin assignments) are implemented via internal NVM and do not affect mechanical or electrical pin compatibility.

SI5335A-B04671-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5335A-B04671-GM FAQ

1.How can I place an order for SI5335A-B04671-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5335A-B04671-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5335A-B04671-GM reliable?

The price and inventory of SI5335A-B04671-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5335A-B04671-GM is usually 5 days.

3.What payment methods are accepted for SI5335A-B04671-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5335A-B04671-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5335A-B04671-GM?

SI5335A-B04671-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5335A-B04671-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5335A-B04671-GM?

For technical support, including SI5335A-B04671-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5335A-B04671-GM requirements.

6.How does Aetrix verify that SI5335A-B04671-GM is sourced from the original manufacturer or authorized distributors?

All SI5335A-B04671-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5335A-B04671-GM meets industry standards.

7.What is the process for return or replacement of SI5335A-B04671-GM?

All SI5335A-B04671-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5335A-B04671-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5335A-B04671-GM part is unused and in its original packaging.

Return procedure for SI5335A-B04671-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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