Skyworks Solutions Inc. SI5335A-B05865-GMR

Overview

SI5335A-B05865-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC featuring MultiSynth fractional synthesis. It delivers four independent, non-integer-related output frequencies up to 350 MHz with 0 ppm frequency synthesis error, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and dual selectable PLL loop bandwidths (475 kHz / 1.6 MHz). It is deployed in high-speed serial interface timing for PCIe switch cards and FPGA-based telecom line cards.

For engineers reviewing the SI5335A-B05865-GMR datasheet, SI5335A-B05865-GMR pinout, SI5335A-B05865-GMR application, or SI5335A-B05865-GMR equivalent, key selection criteria include differential output format support (LVPECL/LVDS/HCSL/CML), per-output voltage configuration (1.5/1.8/2.5/3.3 V), loss-of-signal alarm functionality, and factory-programmed pin-selectable device configurations for multi-plan operation.

Technical Context

The SI5335A-B05865-GMR integrates a single PLL with two configurable loop bandwidths (475 kHz for DSL jitter attenuation; 1.6 MHz for PCIe Gen 3/4) and four independent MultiSynth fractional dividers-each driving one of four output banks. Input flexibility includes 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references.

Each output bank supports either one differential pair or two single-ended signals, with programmable driver type (LVPECL, LVDS, CML, HCSL, CMOS, SSTL, HSTL), output voltage (1.5/1.8/2.5/3.3 V), and slew rate control. Five multi-function pins (P1–P3, P5, P6) enable spread spectrum control (SSENB), master/output enables (OEB), frequency plan selection (FS1/FS0), and reset-all configurable via ClockBuilder Pro.

Key Specifications

Pinout & Package

SI5335A-B05865-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are fixed per the Si5335 family; no variant-specific redefinition is documented for this part number.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5332A-D06889-GM and ICS8430I-01T, the SI5335A-B05865-GMR uniquely balances factory-programmable pin control, 350 MHz capability, PCIe Gen 4 compliance, and loss-of-signal monitoring-making it optimal for industrial and telecom timing where hardware-strapped configurability and robustness are prioritized over field updates or ultra-low jitter.

Availability

SI5335A-B05865-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, FPGA clocking, broadcast video synchronization, and DSLAM jitter attenuation requiring stable component supply, long-term lifecycle assurance, and guaranteed factory programming.

Supply support for SI5335A-B05865-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line was designed to replace multiple discrete clock sources with a single, software-configurable, pin-flexible timing IC-targeting high-speed serial interface timing in datacenter, telecom, and broadcast infrastructure.

FAQ

What is the factory-programmed configuration of the SI5335A-B05865-GMR?

The SI5335A-B05865-GMR is pre-programmed using Skyworks' ClockBuilder Pro to deliver four specific output frequencies, formats, and voltage levels defined at order time. Its configuration is stored in on-chip NVM and activated via pin strapping (FS1/FS0), eliminating the need for I²C initialization during power-up. This ensures deterministic timing behavior from the first clock edge.

Does the SI5335A-B05865-GMR support PCIe Gen 4 Common Clock architecture?

Yes, the SI5335A-B05865-GMR meets PCIe Gen 4 Common Clock jitter specifications (<0.45 ps RMS, 12 kHz–20 MHz) when configured with 1.6 MHz PLL loop bandwidth and differential outputs (e.g., HCSL or LVDS). It is validated per PCI-SIG requirements and referenced in Skyworks Application Note AN562 for PCIe jitter measurement methodology.

Can the SI5335A-B05865-GMR operate as a pure clock buffer without PLL synthesis?

Yes, the SI5335A-B05865-GMR supports PLL bypass mode, functioning as a low-skew, level-translating clock buffer with 2.5–4 ns input-to-output propagation delay. In this mode, it accepts input frequencies from 5 MHz to 350 MHz and passes them through MultiSynth dividers set to integer-N=1, drawing only 12 mA core current-ideal for jitter-cleaning applications.

How does the loss-of-signal (LOS) feature work on the SI5335A-B05865-GMR?

The SI5335A-B05865-GMR asserts its open-drain LOS pin low within 2.6–5 µs of detecting absence of a valid input clock on XA/XB. The release time is 0.01–1 µs after clock restoration. This fast, hardware-monitored alarm enables real-time failover in telecom and broadcast systems without software polling or external comparators.

What output voltage options are supported per bank on the SI5335A-B05865-GMR?

The SI5335A-B05865-GMR supports independent output buffer supply voltages of 1.5 V, 1.8 V, 2.5 V, or 3.3 V on each of its four VDDO pins (VDDO0–VDDO3). This allows simultaneous generation of LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) signals from a single device-eliminating external level translators in mixed-voltage systems.