Skyworks Solutions Inc. SI5335B-B04103-GM

Overview

SI5335B-B04103-GM from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC supporting four independent non-integer-related frequencies up to 350 MHz. It features MultiSynth fractional divider technology with 0 ppm synthesis error, PCIe Gen 1–4 common clock compliance, and dual selectable PLL loop bandwidths (1.6 MHz / 475 kHz). Used in high-speed serial interface timing for PCIe switch cards and FPGA-based telecom line cards.

For engineers reviewing the SI5335B-B04103-GM datasheet, SI5335B-B04103-GM pinout, SI5335B-B04103-GM application, or SI5335B-B04103-GM equivalent, key selection criteria include differential output jitter (0.7 ps RMS), flexible input support (25/27 MHz crystal or 10–350 MHz differential/CMOS), per-output voltage control (1.5/1.8/2.5/3.3 V), loss-of-signal alarm, and pin-selectable frequency plans.

Technical Context

The SI5335B-B04103-GM implements a single PLL with MultiSynth fractional-N synthesis feeding four independent output banks, each configurable as LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL. Input reference options include on-chip 25 or 27 MHz crystal oscillator or external AC-coupled clocks (10–350 MHz differential, 10–200 MHz CMOS).

It supports two PLL loop bandwidth modes (1.6 MHz for PCIe jitter attenuation, 475 kHz for DSL applications), programmable pin functions (SSENB, RESET, FS[1:0], OEB), and loss-of-signal detection with 2.6–5 µs response time. All outputs are independently voltage- and format-configurable with guaranteed 0 ppm frequency error.

Key Specifications

Pinout & Package

SI5335B-B04103-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (XA/CLKIN), pin numbering proceeds counter-clockwise. Ground pins (GND) occupy positions 11, 12, 15, 16, 17, 18, 19, 20, 21, 22, 23, and 24; VDD pins at 7 and 8; VDDOx supply pins distributed across banks.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5341-A-EVB and ICS8430I-01LG, SI5335B-B04103-GM uniquely balances pin-controlled configurability, 0 ppm synthesis accuracy, and PCIe/DSL dual-mode jitter optimization in a compact 24-QFN - making it ideal for volume production of fixed-configuration timing subsystems.

Availability

SI5335B-B04103-GM is available at Aetrix Electronics and suitable for PCIe switch timing, telecom line card clocking, FPGA-based broadcast video sync, and DSLAM MSAN timing requiring stable component supply, factory-programmed reliability, and long-term lifecycle support.

Supply support for SI5335B-B04103-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The SI5335 family is designed as a highly flexible, web-customizable clock generator/buffer platform targeting high-speed serial interface timing in PCIe, Ethernet, telecom, and broadcast video systems - emphasizing jitter performance, configurability, and rapid deployment.

FAQ

What is the maximum output frequency supported by the SI5335B-B04103-GM?

The SI5335B-B04103-GM supports up to 350 MHz on LVPECL, LVDS, CML, SSTL, and HSTL outputs; 250 MHz on HCSL; and 200 MHz on CMOS outputs. These limits are defined by driver architecture and electrical specifications - exceeding them may violate slew rate, duty cycle, or jitter performance guarantees. The SI5335B-B04103-GM achieves this across all four output banks simultaneously with 0 ppm synthesis error.

Does the SI5335B-B04103-GM support PCIe Gen 4 timing requirements?

Yes, the SI5335B-B04103-GM is PCIe Gen 4 common clock compliant, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) with 1.6 MHz PLL loop bandwidth and 100 MHz HCSL outputs. It meets the PCI-SIG Base Specification 4.0 rev. 0.5 jitter mask without external filtering. The SI5335B-B04103-GM also supports spread spectrum and SRNS modes for full Gen 4 system validation.

How many independent output voltage rails does the SI5335B-B04103-GM support?

The SI5335B-B04103-GM provides four independent output supply pins - VDDO0, VDDO1, VDDO2, and VDDO3 - each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O, 2.5 V PHY, 3.3 V legacy logic) without external level shifters. Each rail powers one output bank (CLK0, CLK1, CLK2, CLK3).

Can the SI5335B-B04103-GM operate without an external crystal?

Yes, the SI5335B-B04103-GM can operate without an external crystal by accepting an external AC-coupled clock input (10–350 MHz differential or 10–200 MHz CMOS) on pins XA/CLKIN and XB/CLKINB. However, if using the internal crystal oscillator, only 25 MHz or 27 MHz fundamental-mode crystals with ≤100 Ω ESR and 18 pF load capacitance are supported. The SI5335B-B04103-GM does not support third-overtone or TCXO inputs.

What is the purpose of the LOS pin on the SI5335B-B04103-GM?

The LOS (Loss-of-Signal) pin on the SI5335B-B04103-GM is an open-drain output that asserts low within 2.6–5 µs of detecting failure on the primary input clock (XA/CLKIN). It signals upstream system controllers to initiate failover or reset sequences. The SI5335B-B04103-GM monitors input amplitude and transition rate - not just presence - ensuring robust detection even under marginal signal conditions.