Skyworks Solutions Inc. SI5335B-B04679-GM

Overview

SI5335B-B04679-GM from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, 0 ppm synthesis error via MultiSynth fractional divider technology, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and operation across –40 to +85 °C. It serves as a single-device replacement for multiple crystal oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335B-B04679-GM datasheet, SI5335B-B04679-GM pinout, SI5335B-B04679-GM application, or SI5335B-B04679-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/DSL jitter performance, exact package mapping (24-QFN), and two factory-validated alternative parts for clock tree design and BOM optimization.

Technical Context

The SI5335B-B04679-GM integrates a single PLL with two selectable loop bandwidths (1.6 MHz or 475 kHz) and four independent MultiSynth fractional dividers per output bank, enabling simultaneous synthesis of unrelated frequencies without integer constraints. Its architecture supports both clock generator mode (45 mA core current) and low-power buffer mode (12 mA core current) with PLL bypass.

Input flexibility includes differential (10–350 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or 25/27 MHz crystal reference; outputs support LVPECL/LVDS/CML (1–350 MHz), HCSL (1–250 MHz), CMOS (1–200 MHz), and SSTL/HSTL (1–350 MHz), each configurable for voltage (1.5/1.8/2.5/3.3 V) and format independently.

Key Specifications

Pinout & Package

SI5335B-B04679-GM is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5335 family specification and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5332A-D05889-GM, SI5335B-B04679-GM offers lower cost, smaller footprint, and sufficient jitter performance for PCIe Gen 3/4, while ICS853S01AGI-01LFT provides no synthesis or jitter cleanup-making it viable only for static fanout, not dynamic clock tree generation.

Availability

SI5335B-B04679-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, Ethernet switch/router clocking, and telecom line card synchronization requiring stable component supply, long-term lifecycle assurance, and factory-programmed configuration traceability.

Supply support for SI5335B-B04679-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5335 product line was designed for high-flexibility, any-frequency clock generation in datacenter, networking, and broadcast equipment where multi-protocol timing convergence and PCIe compliance are mandatory.

FAQ

What is the primary function of the SI5335B-B04679-GM in a PCIe Gen 4 system?

The SI5335B-B04679-GM serves as a common clock generator delivering four synchronized, low-jitter reference clocks (e.g., 100 MHz HCSL) to PCIe Gen 4 endpoints and root complexes. It meets PCIe Base Spec 4.0 jitter limits (0.15–0.45 ps RMS) and supports spread spectrum to reduce EMI, making SI5335B-B04679-GM critical for maintaining signal integrity in high-speed serial links.

Does the SI5335B-B04679-GM support crystal oscillator input, and if so, what frequencies?

Yes, the SI5335B-B04679-GM supports on-chip crystal oscillator input at exactly 25 MHz or 27 MHz, with internal 18 pF load capacitance and ESR tolerance up to 100 Ω (25 MHz) or 75 Ω (27 MHz). This eliminates external oscillator components and simplifies board layout while maintaining SI5335B-B04679-GM's 0 ppm synthesis accuracy.

How many independent output voltage supplies does the SI5335B-B04679-GM support, and why does that matter?

The SI5335B-B04679-GM supports four independent output supply rails (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage ASICs, FPGAs, and PHYs (e.g., 1.8 V LVDS + 3.3 V CMOS on same device) without external level shifters-reducing BOM cost and board area while preserving SI5335B-B04679-GM's signal integrity.

Can the SI5335B-B04679-GM operate in clock buffer mode, and what are its power advantages?

Yes, the SI5335B-B04679-GM supports PLL-bypass clock buffer mode with typical core current of 12 mA-less than 27% of its 45 mA clock generator mode consumption. In this mode, SI5335B-B04679-GM passes through and fans out an input clock with <4 ns propagation delay and maintains loss-of-signal detection, ideal for low-power timing distribution where frequency translation isn't required.

What user-assignable control pins are available on the SI5335B-B04679-GM, and how are they used?

The SI5335B-B04679-GM provides five user-assignable pins (P1, P2, P3, P5, P6) supporting functions including spread spectrum enable (SSENB), master/output enable (OEB_all or OEB0–OEB3), frequency plan selection (FS1/FS0), and device reset. These pins allow hardware-driven configuration changes without I²C reprogramming-enabling SI5335B-B04679-GM to replace up to three discrete clock ICs in field-upgradable systems.