Skyworks Solutions Inc. SI5335B-B04743-GMR

Overview

SI5335B-B04743-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC supporting four independent, non-integer-related frequencies up to 350 MHz. It features MultiSynth fractional divider technology with 0 ppm synthesis error, PCIe Gen 1–4 common clock compliance, and dual selectable PLL loop bandwidths (1.6 MHz / 475 kHz). It serves in high-jitter-sensitivity applications such as PCIe root complex timing and Ethernet switch clock distribution.

For engineers reviewing the SI5335B-B04743-GMR datasheet, SI5335B-B04743-GMR pinout, SI5335B-B04743-GMR application, or SI5335B-B04743-GMR equivalent, key selection criteria include its 0.7 ps RMS phase jitter (12 kHz–20 MHz), flexible output format support (LVPECL/LVDS/HCSL/CMOS/SSTL), 24-QFN package, loss-of-signal alarm, and five user-assignable control pins for spread spectrum enable, reset, and frequency plan selection.

Technical Context

The SI5335B-B04743-GMR integrates a single PLL with two configurable loop bandwidth options (1.6 MHz for PCIe jitter attenuation; 475 kHz for DSL jitter filtering) and four independent MultiSynth fractional dividers - each driving one of four output banks. Input flexibility includes differential (10–350 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or crystal (25/27 MHz) references.

All outputs are independently configurable for format (LVPECL, LVDS, CML, HCSL, CMOS, SSTL, HSTL), voltage (1.5/1.8/2.5/3.3 V), and enable state. The device supports three pin-selectable configurations and includes a dedicated LOS (loss-of-signal) alarm output (Pin 8) with sub-5 µs detection time.

Key Specifications

Pinout & Package

SI5335B-B04743-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad (GND). Pin assignments follow the standard Si5335 top-view layout: Pins 1–2 = XA/CLKIN & XB/CLKINB (differential input); Pins 3–4 = CLK2B & CLK2A; Pins 5–6 = VDDO2 & VDDO1; Pins 7–8 = CLK1B & CLK1A; Pins 9–10 = VDD & VDD; Pins 11–12 = CLK3A & CLK3B; Pin 13 = LOS; Pins 14–15 = VDDO0 & CLK0B; Pins 16–17 = CLK0A & RSVD_GND; Pins 18–24 = VDDO3, GND, GND, P1, P2, P3, P5, P6.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with SI5335B-B04743-GMR, the Si5345B-D06789-GM offers greater output count and lower jitter but demands more complex configuration and higher cost; the ICS8430I-01T provides simpler implementation for fixed-rate systems but lacks synthesis flexibility, spread spectrum, and PCIe certification.

Availability

SI5335B-B04743-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, 10/25 GbE switch timing, and broadcast video synchronization requiring stable component supply, factory-programmed configuration, and long-term lifecycle support.

Supply support for SI5335B-B04743-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, industrial, and aerospace markets.

The Si5335 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and telecom standards - designed to replace multiple discrete timing components with a single programmable IC.

FAQ

What is the primary function of the SI5335B-B04743-GMR in a PCIe Gen 4 system?

The SI5335B-B04743-GMR serves as a quad-output, spread-spectrum-capable clock generator that delivers four independent, low-jitter reference clocks (e.g., 100 MHz HCSL) to PCIe Gen 4 endpoints and root complexes. It meets PCIe Gen 4 common clock jitter requirements (≤0.45 ps RMS, ≤33.6 ps pk-pk) using its 1.6 MHz PLL bandwidth and patented MultiSynth technology - eliminating the need for multiple discrete oscillators while ensuring system-level timing compliance. SI5335B-B04743-GMR is factory-configured for this use case.

Does the SI5335B-B04743-GMR support crystal input, and what frequencies are qualified?

Yes, the SI5335B-B04743-GMR supports on-chip crystal oscillator circuitry for 25 MHz and 27 MHz fundamental-mode crystals. Both frequencies are fully qualified per Skyworks' crystal specifications: 25 MHz crystals require 18 pF load capacitance and ≤100 Ω ESR; 27 MHz crystals require 18 pF load capacitance and ≤75 Ω ESR. SI5335B-B04743-GMR uses these references to synthesize all output frequencies with zero ppm error - no external oscillator is needed.

How many independent output voltage supplies does the SI5335B-B04743-GMR support, and why does it matter?

The SI5335B-B04743-GMR supports four independent output buffer supply rails (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous interfacing with mixed-voltage components - for example, driving 1.8 V LVDS SerDes, 2.5 V SSTL memory controllers, and 3.3 V management MCUs from a single IC. SI5335B-B04743-GMR eliminates level-shifter ICs and simplifies power delivery in heterogeneous timing architectures.

Can the SI5335B-B04743-GMR operate in clock buffer mode, and what are the benefits?

Yes, the SI5335B-B04743-GMR supports PLL bypass (buffer) mode, where the input clock is distributed directly to outputs with minimal added jitter (2.5–4 ns propagation delay). In this mode, core supply current drops to 12 mA - significantly reducing power and heat. SI5335B-B04743-GMR retains full output format and voltage configurability, making it ideal for low-power clock fanout or jitter-sensitive bypass paths in hybrid timing trees.

What is the role of the LOS (loss-of-signal) pin on the SI5335B-B04743-GMR, and how fast does it respond?

The LOS (Pin 13) is an active-low, open-drain output that signals loss of valid input clock on XA/XB within 2.6–5 µs. It drives external monitoring circuitry or processor GPIOs to trigger failover, system reset, or alarm logging. SI5335B-B04743-GMR's fast LOS response enables real-time fault detection in carrier-grade and broadcast systems where timing continuity is mission-critical - and the pin remains functional across all operating modes and configurations.