Skyworks Solutions Inc. SI5335B-B05132-GMR

Overview

SI5335B-B05132-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis, delivering four independent non-integer-related frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and configurable LVPECL/LVDS/HCSL/CMOS outputs - used in high-speed serial interface timing for FPGA and processor clocking.

For engineers reviewing the SI5335B-B05132-GMR datasheet, SI5335B-B05132-GMR pinout, SI5335B-B05132-GMR application, or SI5335B-B05132-GMR equivalent, this device supports factory-programmed configurations via ClockBuilder Pro, offers dual PLL loop bandwidths (475 kHz / 1.6 MHz), loss-of-signal detection, and five user-assignable control pins for spread spectrum, reset, and frequency plan selection.

Technical Context

The SI5335B-B05132-GMR implements a single high-performance PLL with patented MultiSynth fractional dividers per output bank, enabling independent synthesis of four frequencies without integer constraints. It supports both clock generator mode (full synthesis) and buffer mode (PLL bypass), with input flexibility across crystal (25/27 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), and differential (10–350 MHz) references.

Its architecture includes four output banks - each configurable as one differential pair or two single-ended outputs - with per-driver voltage selection (1.5/1.8/2.5/3.3 V), programmable slew rate, and independent enable/control logic. The device integrates loss-of-signal alarm, PCIe-compliant spread spectrum, and two selectable PLL loop bandwidths optimized for jitter attenuation in PCIe and DSL applications.

Key Specifications

Pinout & Package

SI5335B-B05132-GMR uses a 24-lead QFN package (4 mm × 4 mm) with exposed thermal pad. Pin functions are fully documented in Skyworks Rev. 1.4 datasheet, including dual reference inputs, four differential output banks, five multi-function control pins (P1–P6), LOS alarm, and dedicated power/ground terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5332B-D05132-GM and ICS8430I-01T, SI5335B-B05132-GMR uniquely balances web-customizability, 4-output flexibility, PCIe Gen 4 compliance, and QFN-24 footprint - making it the preferred choice for new industrial and communications designs requiring field-programmable timing without over-spec'ing.

Availability

SI5335B-B05132-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server timing, FPGA-based telecom line cards, and 10 GbE switch/router designs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5335B-B05132-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5335 family was designed specifically for high-speed serial interface timing - targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems requiring flexible, low-jitter, multi-output clock generation in compact packages.

FAQ

What is the primary function of the SI5335B-B05132-GMR?

The SI5335B-B05132-GMR is a quad-output, any-frequency clock generator/buffer IC that synthesizes four independent, non-integer-related clock frequencies up to 350 MHz using Skyworks' MultiSynth fractional divider technology. It serves as a timing solution for PCIe, Ethernet, FPGA, and broadcast video systems - replacing multiple oscillators and buffers with a single, web-configurable device.

Does the SI5335B-B05132-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335B-B05132-GMR meets PCIe Gen 4 common clock jitter specifications (≤0.45 ps RMS, 12 kHz–20 MHz) when configured with 1.6 MHz PLL loop bandwidth and HCSL outputs. It is explicitly listed as PCIe Gen 1/2/3/4 common clock compliant and SRNS-compliant in the official Skyworks datasheet Rev. 1.4.

How many output configurations can be stored and selected on the SI5335B-B05132-GMR?

The SI5335B-B05132-GMR supports up to three independent, pin-selectable device configurations. These are selected using the FS[1:0] control pins (P5 and P6), allowing a single device to operate as three different clock generators or buffers depending on system state - reducing BOM count and design complexity.

What input reference sources does the SI5335B-B05132-GMR accept?

The SI5335B-B05132-GMR accepts multiple reference inputs: 25 MHz or 27 MHz crystals (internally terminated), CMOS clocks (10–200 MHz), SSTL/HSTL clocks (10–350 MHz), and differential clocks (LVDS/LVPECL/CML/HCSL, 10–350 MHz). Input flexibility enables use across diverse system architectures without external conditioning circuitry.

Is the SI5335B-B05132-GMR pin-compatible with other Si5335 variants?

Yes, all Si5335 variants - including SI5335B-B05132-GMR - share the same 24-QFN package and pinout. Differences lie in factory-programmed configuration (e.g., output frequencies, formats, control pin assignments), not physical layout. This ensures hardware compatibility across custom variants during design reuse or revision.