Skyworks Solutions Inc. SI5335B-B05154-GMR

Overview

SI5335B-B05154-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis, delivering four independent non-integer-related frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and dual selectable PLL loop bandwidths (1.6 MHz / 475 kHz) - deployed in high-speed Ethernet switch/router and FPGA clocking systems.

For engineers reviewing the SI5335B-B05154-GMR datasheet, SI5335B-B05154-GMR pinout, SI5335B-B05154-GMR application, or SI5335B-B05154-GMR equivalent, key selection criteria include differential output format support (LVPECL/LVDS/HCSL/CML), per-output voltage programmability (1.5/1.8/2.5/3.3 V), loss-of-signal alarm, and pin-selectable frequency plan control for PCIe jitter attenuation and DSL timing applications.

Technical Context

The SI5335B-B05154-GMR implements a single PLL with patented MultiSynth fractional divider architecture, enabling independent synthesis of all four output banks without integer constraints. It supports both clock generator mode (45 mA core current) and low-power buffer mode (12 mA core current) with PLL bypass.

Input flexibility includes 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references. Output drivers are independently configurable per bank for LVPECL, LVDS, CML, HCSL, CMOS, SSTL, or HSTL formats with per-bank VDDO supply (1.4–3.63 V).

Key Specifications

Pinout & Package

SI5335B-B05154-GMR uses a 24-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet Figure 1 (Top View).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345B-D05154-GM and ICS8430I-01LG, SI5335B-B05154-GMR uniquely balances web-customizable any-frequency synthesis, PCIe Gen4 compliance, and dual-loop-bandwidth jitter filtering - making it the optimal choice for scalable, multi-standard timing in next-gen networking and compute platforms.

Availability

SI5335B-B05154-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 1–4 clocking, and FPGA processor clock distribution requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for SI5335B-B05154-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The SI5335 family is designed as a highly flexible, web-customizable clock generator/buffer platform targeting high-speed serial interface timing - specifically engineered to replace multiple discrete oscillators and clock ICs in PCIe, Ethernet, and FPGA-based systems.

FAQ

What is the primary function of the SI5335B-B05154-GMR in a system?

The SI5335B-B05154-GMR serves as a quad-output clock generator/buffer IC that synthesizes four independent, non-integer-related frequencies up to 350 MHz using Skyworks' MultiSynth fractional divider technology. Its primary function is to replace multiple discrete oscillators and clock ICs while delivering 0.7 ps RMS phase jitter and PCIe Gen 1–4 compliance - directly implemented in SI5335B-B05154-GMR-based designs for Ethernet switches and server motherboards.

Does the SI5335B-B05154-GMR support spread spectrum clocking (SSC)?

Yes, the SI5335B-B05154-GMR supports PCIe-compliant spread spectrum clocking with a default down-spread of –0.5% at 31.5 kHz modulation rate. The SSENB control pin enables hardware activation, and SSC parameters are configurable via ClockBuilder Pro. This feature is validated for SI5335B-B05154-GMR in PCIe Gen 1/2/3 common clock mode to reduce electromagnetic interference without violating jitter limits.

What output voltage levels does the SI5335B-B05154-GMR support per bank?

The SI5335B-B05154-GMR supports independent output supply voltages per bank (VDDO0–VDDO3) ranging from 1.4 V to 3.63 V, enabling selectable I/O levels of 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage components - for example, driving 1.8 V LVDS SerDes and 3.3 V CMOS microcontrollers simultaneously - a capability confirmed in SI5335B-B05154-GMR's electrical specifications tables.

How many pin-selectable frequency configurations does the SI5335B-B05154-GMR support?

The SI5335B-B05154-GMR supports three independent, pin-selectable device configurations via FS[1:0] and master enable inputs. These allow hardware-switched selection among pre-programmed frequency plans - for instance, one configuration for PCIe Gen3 (100 MHz), another for Gen4 (100 MHz with tighter jitter), and a third for Ethernet (156.25 MHz) - all stored and activated without firmware intervention in the SI5335B-B05154-GMR.

Is the SI5335B-B05154-GMR qualified for industrial temperature operation?

Yes, the SI5335B-B05154-GMR is fully specified and tested over an ambient temperature range of –40 °C to +85 °C, meeting industrial-grade reliability requirements. All electrical parameters - including 0.7 ps RMS jitter, 45 mA core current in generator mode, and loss-of-signal detection - are guaranteed across this range per Skyworks Rev. 1.4 datasheet Section 1, making SI5335B-B05154-GMR suitable for telecom line cards and industrial embedded systems.