Skyworks Solutions Inc. SI5335B-B05156-GMR

Overview

SI5335B-B05156-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator supporting four independent non-integer-related frequencies up to 350 MHz, with LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL output formats, 0.7 ps RMS phase jitter, and PCIe Gen 1–4 common clock compliance - deployed in high-speed serial interconnect timing for server backplanes and FPGA-based telecom line cards.

For engineers reviewing the SI5335B-B05156-GMR datasheet, SI5335B-B05156-GMR pinout, SI5335B-B05156-GMR application, or SI5335B-B05156-GMR equivalent, key selection criteria include differential output jitter performance (0.7 ps RMS), dual PLL loop bandwidth options (475 kHz / 1.6 MHz), MultiSynth fractional synthesis accuracy (0 ppm error), and pin-selectable device configuration support for PCIe jitter attenuation and DSL applications.

Technical Context

The SI5335B-B05156-GMR implements a single PLL architecture with four independent MultiSynth fractional dividers per output bank, enabling any-frequency synthesis without integer constraints. Input reference flexibility includes 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) sources.

Each of the four output banks supports either one differential pair or two single-ended outputs, with independent voltage control (1.5/1.8/2.5/3.3 V) and format selection. Loss-of-signal detection, spread-spectrum enable (SSENB), frequency plan selection (FS1/FS0), and master/output-enable pins are implemented via five user-assignable control pins (P1–P3, P5–P6).

Key Specifications

Pinout & Package

SI5335B-B05156-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow the standard Si5335 top-view layout, including dual differential inputs (XA/CLKIN, XB/CLKINB), four differential output pairs (CLK0A/B through CLK3A/B), three dedicated control pins (P1, P2, P3), two multi-function pins (P5, P6), loss-of-signal indicator (LOS), power (VDD, VDDO0–VDDO3), and ground (GND) terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345B-D05156-GM and ICS8430I-01T, SI5335B-B05156-GMR uniquely balances web-customizable any-frequency synthesis, PCIe Gen 4 compliance, and industrial temperature operation in a compact 24-QFN - making it optimal for cost-sensitive, high-mix telecom and server timing designs requiring field-programmable flexibility without overengineering.

Availability

SI5335B-B05156-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, DSLAM line cards, and broadcast video timing systems requiring stable component supply, long-term lifecycle assurance, and factory-configured delivery.

Supply support for SI5335B-B05156-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly flexible, web-customizable clock generation for high-speed serial interfaces - designed specifically to replace multiple discrete oscillators and buffers in PCIe, Ethernet, telecom, and video systems.

FAQ

What is the primary function of the SI5335B-B05156-GMR?

The SI5335B-B05156-GMR is a quad-output, any-frequency clock generator that synthesizes four independent, non-integer-related clock signals up to 350 MHz using Skyworks' MultiSynth fractional divider technology. It serves as both a clock generator and configurable buffer, supporting PCIe Gen 1–4, DSL, broadcast video, and FPGA timing applications with 0 ppm synthesis error and 0.7 ps RMS jitter.

Does the SI5335B-B05156-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335B-B05156-GMR is PCIe Gen 4 common clock compliant, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) at 100 MHz HCSL output with 1.6 MHz PLL bandwidth. It meets the PCI-SIG Base Specification 4.0 rev. 0.5 jitter mask for Gen 4 systems and supports spread-spectrum clocking for EMI reduction.

How many output configurations does the SI5335B-B05156-GMR support?

The SI5335B-B05156-GMR supports three independent, pin-selectable device configurations via FS1 and FS0 control pins. This allows a single part number to be used across multiple board revisions or system modes - for example, one config for PCIe Gen 3, another for DSL, and a third for broadcast video - reducing inventory complexity.

What input reference options are supported by the SI5335B-B05156-GMR?

The SI5335B-B05156-GMR accepts multiple input references: 25 MHz or 27 MHz crystals (internal load capacitance 18 pF), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (LVDS/LVPECL/HCSL/CML, 10–350 MHz). No external level-shifting or termination components are required for most configurations.

Is factory customization required to use the SI5335B-B05156-GMR?

No - the SI5335B-B05156-GMR ships with a default configuration but is fully web-customizable via Skyworks' ClockBuilder Pro tool. Users define frequencies, output formats, voltage levels, and control pin functions online; factory-programmed units ship in ≤2 weeks with no minimum order quantity, enabling rapid prototyping and production deployment.