Skyworks Solutions Inc. SI5335B-B05222-GMR

Overview

SI5335B-B05222-GMR from Skyworks Solutions is a quad-output, any-frequency clock generator IC with four independent MultiSynth fractional dividers, supporting up to 350 MHz differential or 200 MHz single-ended outputs, 0 ppm synthesis error, 0.7 ps RMS phase jitter, and PCIe Gen 1–4 common-clock compliance - deployed in high-speed serial interface timing for server backplanes and FPGA-based telecom line cards.

For engineers reviewing the SI5335B-B05222-GMR datasheet, SI5335B-B05222-GMR pinout, SI5335B-B05222-GMR application, or SI5335B-B05222-GMR equivalent, key selection criteria include its dual-loop-bandwidth (475 kHz / 1.6 MHz) PLL architecture, pin-selectable frequency plans, loss-of-signal alarm, and support for LVPECL/LVDS/HCSL/CMOS/SSTL output formats across four banks with independent VDDO voltage control.

Technical Context

The SI5335B-B05222-GMR implements a single PLL with two selectable loop bandwidths (475 kHz or 1.6 MHz) and four independent MultiSynth fractional-N synthesizers per output bank, enabling simultaneous generation of non-integer-related frequencies without reference multiplication. It accepts differential (10–350 MHz), CMOS (10–200 MHz), or crystal (25/27 MHz) inputs and supports PLL bypass mode for low-latency clock buffering.

Each of its four output banks can be configured as one differential pair or two single-ended signals, with per-bank VDDO supply (1.5/1.8/2.5/3.3 V) and programmable driver format. Five multi-function pins (P1–P3, P5–P6) support spread-spectrum enable, master/output enables, frequency plan selection (FS1/FS0), and reset - all configurable via ClockBuilder Pro web utility.

Key Specifications

Pinout & Package

SI5335B-B05222-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow standard Si5335 layout: differential inputs on Pins 1 (XA/CLKIN) and 2 (XB/CLKINB); four differential output pairs (CLK0A/B through CLK3A/B) distributed across Pins 3–4, 6–7, 10–11, and 13–14; LOS alarm on Pin 8; five multi-function control pins (P1–P3, P5–P6) on Pins 5, 9, 12, 15–16; and dedicated VDD, VDDO, and GND terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-B-GM and ICS8430I-01T, SI5335B-B05222-GMR uniquely balances 4-output any-frequency synthesis, PCIe Gen 4 compliance, pin-selectable configuration, and 4×4 mm QFN footprint - making it the preferred choice for space-constrained, multi-standard timing in servers and telecom hardware.

Availability

SI5335B-B05222-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, Ethernet switch fabric cards, FPGA-based telecom line cards, and broadcast video synchronization systems requiring stable component supply and guaranteed long-term manufacturability.

Supply support for SI5335B-B05222-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line was designed specifically for high-performance, multi-protocol clock generation in datacenter, telecom, and broadcast infrastructure - emphasizing zero-error synthesis, ultra-low jitter, and field-configurable operation without firmware dependency.

FAQ

What is the primary function of the SI5335B-B05222-GMR in a PCIe Gen 4 system?

The SI5335B-B05222-GMR serves as a quad-output, any-frequency clock generator that delivers four independent, low-jitter (≤0.45 ps RMS) HCSL reference clocks compliant with PCIe Gen 4 common-clock specifications. It replaces multiple discrete oscillators and supports spread-spectrum modulation to reduce EMI, while its 1.6 MHz PLL loop bandwidth ensures optimal jitter attenuation for high-speed serial links. SI5335B-B05222-GMR integrates this functionality in a single 4×4 mm QFN package.

Does the SI5335B-B05222-GMR support both clock generator and clock buffer modes?

Yes, the SI5335B-B05222-GMR supports both modes. In clock generator mode, it uses its internal PLL and four MultiSynth fractional-N dividers to synthesize arbitrary frequencies up to 350 MHz. In clock buffer mode (PLL bypass), it routes the input clock directly to outputs with <4 ns propagation delay and no frequency translation - ideal for latency-sensitive applications. SI5335B-B05222-GMR enables mode selection via pin configuration or register setting.

How does the loss-of-signal (LOS) feature work on the SI5335B-B05222-GMR?

The SI5335B-B05222-GMR monitors its differential input (Pins 1/2) and asserts the open-drain LOS pin (Pin 8) within 2.6–5 µs of signal loss. This hardware-based alarm requires no firmware intervention and supports system-level fault detection and failover. The LOS release time is 0.01–1 µs after signal restoration. SI5335B-B05222-GMR's LOS circuit operates independently of PLL lock status and remains functional across all input types (crystal, CMOS, differential).

Can the SI5335B-B05222-GMR generate different output voltages on separate banks?

Yes, SI5335B-B05222-GMR provides independent VDDO supplies for each of its four output banks (VDDO0–VDDO3), supporting 1.5 V, 1.8 V, 2.5 V, or 3.3 V per bank. This allows concurrent LVDS outputs at 1.8 V and CMOS outputs at 3.3 V without level-shifting components. Voltage selection is hardware-configured via external supply routing, and SI5335B-B05222-GMR guarantees full electrical compliance across all supported VDDO ranges per bank.

Is factory customization required to use the SI5335B-B05222-GMR, or can it operate with default settings?

The SI5335B-B05222-GMR ships with factory-programmed configuration stored in on-chip NVM, enabling immediate operation upon power-up without external programming. Default settings include 100 MHz LVDS outputs, 25 MHz crystal input, and 1.6 MHz PLL bandwidth. However, full utilization of its any-frequency capability, pin-selectable frequency plans, and spread-spectrum control requires customization via Skyworks' ClockBuilder Pro web tool - a process that delivers programmed units in under two weeks with no MOQ. SI5335B-B05222-GMR is fully functional out-of-box but optimized via customization.