Skyworks Solutions Inc. SI5335B-B05272-GM

Overview

SI5335B-B05272-GM from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis. It delivers four independent, non-integer-related output frequencies up to 350 MHz (LVPECL/LVDS/CML), supports PCIe Gen 1–4 common clock and SRNS compliance, achieves 0.7 ps RMS phase jitter, and operates across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It serves as a single-device replacement for multiple crystal oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335B-B05272-GM datasheet, SI5335B-B05272-GM pinout, SI5335B-B05272-GM application, or SI5335B-B05272-GM equivalent, key selection criteria include its 0 ppm frequency synthesis error guarantee, dual PLL loop bandwidth options (475 kHz / 1.6 MHz), per-output voltage configurability (1.5/1.8/2.5/3.3 V), loss-of-signal alarm, and five user-assignable control pins for spread spectrum, reset, and frequency plan selection.

Technical Context

The SI5335B-B05272-GM implements four independent MultiSynth fractional dividers driven by a single PLL, enabling simultaneous synthesis of unrelated output frequencies without integer constraints. Each output bank supports differential (LVPECL/LVDS/CML/HCSL) or single-ended (CMOS/SSTL/HSTL) formats with individually selectable VDDO voltages.

It accepts flexible input references: 25/27 MHz crystal, or AC-coupled CMOS/SSTL/HSTL/differential signals from 10–350 MHz. Two configurable PLL loop bandwidths (475 kHz or 1.6 MHz) allow optimization for jitter attenuation in PCIe or DSL applications, while pin-selectable device configurations support three distinct frequency plans without reprogramming.

Key Specifications

Pinout & Package

SI5335B-B05272-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet, with dedicated inputs (XA/CLKIN, XB/CLKINB), four differential output banks (CLK0A/B through CLK3A/B), VDDO supplies per bank, control pins (P1–P6), LOS alarm, and ground/power connections.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5341-B-GM and ICS8430I-01LG, SI5335B-B05272-GM uniquely balances web-based customization, 0 ppm synthesis accuracy, PCIe Gen 4 compliance, and 4-output flexibility at an industrial-grade price point - making it ideal for scalable, multi-standard timing in networking and embedded computing.

Availability

SI5335B-B05272-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch design, 10/25 GbE router timing, and FPGA-based broadcast video equipment requiring stable component supply, factory-programmed configuration, and long-term lifecycle support.

Supply support for SI5335B-B05272-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for communications, automotive, and industrial markets.

The Si5335 product line was designed to replace multiple discrete clock sources with a single, field-configurable, any-frequency generator - targeting high-speed serial interface timing in data centers, telecom infrastructure, and broadcast systems.

FAQ

What is the primary function of the SI5335B-B05272-GM?

The SI5335B-B05272-GM is a quad-output, web-customizable clock generator/buffer IC that synthesizes four independent, non-integer-related frequencies up to 350 MHz using Skyworks' MultiSynth fractional divider technology. It replaces multiple oscillators and clock ICs in PCIe, Ethernet, and FPGA timing applications while guaranteeing 0 ppm frequency synthesis error. Its pin-selectable configurations and flexible I/O formats make SI5335B-B05272-GM suitable for high-density, multi-standard system designs.

Does the SI5335B-B05272-GM support PCIe Gen 4 timing requirements?

Yes, the SI5335B-B05272-GM is PCIe Gen 4 common clock compliant, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) under specified test conditions (100 MHz HCSL outputs, 25 MHz crystal reference, 1.6 MHz PLL loop bandwidth). It also meets PCIe Gen 3 SRNS requirements with ≤0.32 ps RMS jitter. These validated performance metrics ensure SI5335B-B05272-GM satisfies the strict jitter budgets of Gen 4 serial links without external cleanup circuits.

How many output configurations can be stored and selected on the SI5335B-B05272-GM?

The SI5335B-B05272-GM supports three independent, pin-selectable device configurations. Using the FS1 and FS0 control pins, users can choose among three pre-programmed frequency plans - enabling one physical device to serve multiple system states (e.g., different data rates or operational modes) without firmware intervention. This feature is factory-programmed via ClockBuilder Pro and is integral to SI5335B-B05272-GM's role in reducing BOM count and design complexity.

What input reference options does the SI5335B-B05272-GM accept?

The SI5335B-B05272-GM accepts multiple input references: a 25 or 27 MHz fundamental-mode crystal directly connected to XA/XB pins; or AC-coupled external clocks including CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), and differential formats (LVDS/LVPECL/CML/HCSL, 10–350 MHz). The device includes on-chip crystal load capacitance (18 pF) and supports both PLL and PLL-bypass (buffer) modes - making SI5335B-B05272-GM adaptable to diverse system clocking architectures.

Can the SI5335B-B05272-GM generate different output voltage levels simultaneously?

Yes, the SI5335B-B05272-GM provides independent VDDO supplies for each of its four output banks (VDDO0–VDDO3), allowing simultaneous operation at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components - for example, driving 1.8 V FPGA I/O banks and 3.3 V legacy SerDes with separate outputs from the same SI5335B-B05272-GM device - without level shifters or external regulators.