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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5335B-B05272-GMR

Name: SI5335B-B05272-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5335B-B05272-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5335B-B05272-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5335B-B05272-GMR.pdf

Description:: IC 4OUT ANY FREQ <200MHZ 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5335B-B05272-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis. It delivers four independent, non-integer-related output frequencies up to 350 MHz, supports LVPECL/LVDS/HCSL/CMOS/SSTL outputs, achieves 0.7 ps RMS phase jitter, and operates across –40 to +85 °C in PCIe Gen 1–4 and DSL jitter-attenuation systems.

For engineers reviewing the SI5335B-B05272-GMR datasheet, SI5335B-B05272-GMR pinout, SI5335B-B05272-GMR application, or SI5335B-B05272-GMR equivalent, this device enables single-chip replacement of multiple oscillators and clock ICs in high-speed serial interface timing, FPGA/processor clocking, and telecom line card synchronization - with factory-configurable pin-selectable frequency plans and spread-spectrum control.

Technical Context

The SI5335B-B05272-GMR integrates a single PLL with two selectable loop bandwidths (1.6 MHz or 475 kHz) and four independent MultiSynth fractional dividers per output bank, enabling zero-ppm synthesis error across all outputs regardless of frequency combination. Its input accepts 10–350 MHz differential (LVDS/LVPECL/CML/HCSL) or single-ended (CMOS/SSTL/HSTL) clocks, or a 25/27 MHz crystal.

Each of the four output banks supports configurable voltage (1.5/1.8/2.5/3.3 V), format (differential or dual single-ended), and enable logic (global or per-bank). Five multi-function pins (P1–P3, P5, P6) support SSENB, RESET, FS[1:0], and OEB functions, while LOS provides loss-of-signal detection with 2.6–5 µs response time.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	Four banks: each supports one differential pair (e.g., CLK0A/CLK0B) or two single-ended outputs - enabling up to 4 differential or 8 single-ended clocks simultaneously.
Max Output Frequency	350 MHz for LVPECL/LVDS/CML/SSTL/HSTL; 250 MHz for HCSL; 200 MHz for CMOS - covers PCIe Gen 4 (100 MHz), 10GbE (156.25 MHz), and Fibre Channel (212.5 MHz) requirements.
Phase Jitter (RMS)	0.7 ps (12 kHz–20 MHz) in clock generator mode with 1.6 MHz PLL bandwidth - meets PCIe Gen 3 SRNS (≤0.32 ps) and Gen 4 (≤0.45 ps) common-clock jitter limits.
Input Flexibility	Accepts 25/27 MHz crystal, or AC-coupled 10–350 MHz differential (LVDS/LVPECL/CML/HCSL) or single-ended (CMOS/SSTL/HSTL) reference - eliminates need for external buffer or level shifter in most systems.
Power Supply	Single 1.8/2.5/3.3 V core supply (±10% tolerance); independent VDDOx per bank (1.4–3.63 V) - simplifies power sequencing and supports mixed-voltage system interfaces.
Operating Temp	–40 to +85 °C ambient - qualified for industrial and telecom infrastructure applications including MSAN, DSLAM, and line cards.

Pinout & Package

SI5335B-B05272-GMR is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Rev. 1.4 datasheet and include dual differential inputs (XA/CLKIN, XB/CLKINB), four differential output pairs (CLK0A/B through CLK3A/B), five programmable control pins (P1–P3, P5, P6), LOS alarm output, and dedicated VDD/VDDO/GND rails.

Pin/Terminal	Circuit Role	Design Meaning
1, 2 (XA/CLKIN, XB/CLKINB)	Differential reference input	Accepts 10–350 MHz LVDS/LVPECL/CML/HCSL; internal 100 Ω termination enabled - supports direct connection to oscillator or PHY without external resistors.
3–4, 6–7, 10–11, 13–14 (CLK0A/B to CLK3A/B)	Differential clock outputs	Four independent banks; each pair configurable as LVPECL/LVDS/HCSL/CML with per-bank VDDO voltage selection - enables mixed-format clock distribution to multiple ICs.
5, 8, 9, 12, 15–16 (P1–P3, P5, P6, LOS)	Multi-function control I/O	P1–P3/P5/P6 support OEB, SSENB, FS[1:0], RESET; LOS asserts low on input loss - allows hardware-based frequency plan switching and system-level fault monitoring without MCU intervention.
17–24 (VDD, VDDO0–3, GND, RSVD_GND)	Power and ground terminals	Dedicated VDD core and four VDDO supplies (one per output bank); RSVD_GND is internally connected to substrate - ensures clean power delivery and minimizes crosstalk between output banks.

Key Features

Feature	Design Value
Web-customizable configuration	Factory-programmed via ClockBuilder Pro in ≤2 weeks with no MOQ - eliminates NRE and enables rapid prototyping of unique frequency plans for PCIe, Ethernet, or broadcast video systems.
Three pin-selectable configurations	Hardware-switched between three preloaded frequency/enable/output-format settings using FS[1:0] pins - supports field-upgradable timing modes without firmware update or reprogramming.
PCIe Gen 1–4 common-clock compliance	Validated jitter performance (≤0.45 ps RMS) at 100 MHz HCSL output with 1.6 MHz PLL BW - satisfies PCIe Base Spec 4.0 timing requirements for root complex and endpoint devices.
Loss-of-signal (LOS) detection	2.6–5 µs detection latency with automatic holdover behavior - maintains system stability during transient reference failures in telecom and storage applications.
Low-power operation	45 mA core current in clock generator mode; 12 mA in buffer (PLL bypass) mode - reduces thermal load and enables use in space-constrained 1U servers and embedded modules.

Applications

PCI Express Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to PCIe Gen 4 root complex and endpoints in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (0.45 ps RMS) HCSL clocks with spread-spectrum support. Use Value: Replaces four discrete oscillators while meeting PCIe 4.0 common-clock jitter mask and reducing board area by >60%.	Use Scenario: Generating 156.25 MHz SerDes clocks and 250 MHz packet processing clocks in 10GbE line cards. IC Role / Device Role / Timing Role: Configurable clock buffer/generator supporting LVDS (156.25 MHz) and CMOS (250 MHz) outputs from single 25 MHz crystal. Use Value: Eliminates need for separate jitter cleaners and level translators, cutting BOM cost and improving timing margin across multi-rate PHYs.
Broadcast Video Synchronization	Telecom Line Card Timing
Use Scenario: Distributing frame-locked 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks to SDI encoders/decoders in broadcast routers. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE ST 292/425 rates with 0 ppm error via MultiSynth fractional division. Use Value: Ensures sub-pixel timing accuracy across multi-channel video paths without external VCXOs or trimming components.	Use Scenario: Providing jitter-attenuated 70.656 MHz and 155.52 MHz clocks for DSLAM and OC-12 line interfaces. IC Role / Device Role / Timing Role: Dual-loop-bandwidth (475 kHz) clock generator meeting ITU-T G.823/G.824 wander and jitter specs. Use Value: Achieves <2 ps RMS random jitter in 10 kHz–400 kHz band - exceeds DSL jitter attenuation requirements while sharing one device across multiple line cards.

PCI Express Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to PCIe Gen 4 root complex and endpoints in server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (0.45 ps RMS) HCSL clocks with spread-spectrum support.

Use Value: Replaces four discrete oscillators while meeting PCIe 4.0 common-clock jitter mask and reducing board area by >60%.

Use Scenario: Generating 156.25 MHz SerDes clocks and 250 MHz packet processing clocks in 10GbE line cards.

IC Role / Device Role / Timing Role: Configurable clock buffer/generator supporting LVDS (156.25 MHz) and CMOS (250 MHz) outputs from single 25 MHz crystal.

Use Value: Eliminates need for separate jitter cleaners and level translators, cutting BOM cost and improving timing margin across multi-rate PHYs.

Broadcast Video Synchronization

Telecom Line Card Timing

Use Scenario: Distributing frame-locked 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks to SDI encoders/decoders in broadcast routers.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE ST 292/425 rates with 0 ppm error via MultiSynth fractional division.

Use Value: Ensures sub-pixel timing accuracy across multi-channel video paths without external VCXOs or trimming components.

Use Scenario: Providing jitter-attenuated 70.656 MHz and 155.52 MHz clocks for DSLAM and OC-12 line interfaces.

IC Role / Device Role / Timing Role: Dual-loop-bandwidth (475 kHz) clock generator meeting ITU-T G.823/G.824 wander and jitter specs.

Use Value: Achieves <2 ps RMS random jitter in 10 kHz–400 kHz band - exceeds DSL jitter attenuation requirements while sharing one device across multiple line cards.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-D-GM	Four-output, lower max frequency (200 MHz), integrated crystal option, higher typical jitter (1.1 ps RMS)	Better suited for cost-sensitive industrial MCU clocking where <200 MHz suffices and crystal integration reduces component count	Select when crystal integration and lower frequency range outweigh need for 350 MHz capability and sub-0.8 ps jitter.
ICS8430I-01LG	Quad LVDS output only, fixed 100/125/156.25 MHz outputs, no fractional synthesis, no programmable pins	Limited to fixed-frequency applications like standard Ethernet PHYs; lacks PCIe spread spectrum or multi-plan flexibility	Choose only for simple, static clock fanout where frequency agility and hardware configurability are unnecessary.

Compared with Si5338A-D-GM and ICS8430I-01LG, the SI5335B-B05272-GMR uniquely combines 350 MHz synthesis, 0.7 ps RMS jitter, three hardware-selectable configurations, and web-based customization - making it optimal for high-performance, multi-standard systems requiring field-reconfigurable timing.

Availability

SI5335B-B05272-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10GbE switch fabric designs, and telecom line card timing applications requiring stable component supply, long-term lifecycle assurance, and factory-programmed configuration traceability.

Supply support for SI5335B-B05272-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5335 family is engineered for high-speed serial interface timing - delivering ultra-low jitter, multi-frequency synthesis, and hardware-flexible configuration to replace discrete clock trees in PCIe, Ethernet, Fibre Channel, and broadcast systems.

FAQ

What is the maximum output frequency supported by the SI5335B-B05272-GMR?

The SI5335B-B05272-GMR supports up to 350 MHz on LVPECL, LVDS, CML, SSTL, and HSTL outputs; 250 MHz on HCSL; and 200 MHz on CMOS. These limits are validated per Skyworks Rev. 1.4 datasheet Table 4 and enable full coverage of PCIe Gen 4 (100 MHz), 10GbE (156.25 MHz), and Fibre Channel (212.5 MHz) timing requirements. The SI5335B-B05272-GMR achieves this using its patented MultiSynth fractional divider architecture with zero-ppm synthesis error.

Does the SI5335B-B05272-GMR support spread-spectrum clocking (SSC)?

Yes, the SI5335B-B05272-GMR supports PCIe-compliant spread-spectrum clocking via the SSENB pin. When asserted, it applies –0.45% to –0.5% down-spread modulation at 31.5 kHz (default), meeting PCI-SIG specifications for EMI reduction. This function is hardware-controlled and does not require register programming. The SI5335B-B05272-GMR's SSC implementation is validated in Table 3 and Section 5 of the datasheet, and its jitter impact is characterized in Tables 8 and 9.

Can the SI5335B-B05272-GMR operate without an external crystal?

Yes, the SI5335B-B05272-GMR can operate without an external crystal by accepting an external AC-coupled clock input (10–350 MHz) on pins XA/CLKIN and XB/CLKINB. It also supports CMOS, SSTL, or HSTL single-ended inputs (10–200 MHz). Crystal operation is optional and limited to 25 or 27 MHz per Tables 6 and 7. The SI5335B-B05272-GMR's flexible input architecture eliminates dependency on crystal components in systems with existing low-jitter reference sources.

How many independent output voltage supplies does the SI5335B-B05272-GMR support?

The SI5335B-B05272-GMR supports five independent voltage supplies: one core VDD (1.8/2.5/3.3 V) and four dedicated VDDOx rails (VDDO0–VDDO3), each configurable from 1.4 V to 3.63 V. This allows mixed-signal systems to drive LVPECL (2.5 V), LVDS (2.5/3.3 V), and CMOS (1.8 V) loads simultaneously from a single device. Each VDDO rail powers one output bank, ensuring noise isolation and level compatibility - a key feature confirmed in Table 1 and Section 3.10 of the SI5335B-B05272-GMR datasheet.

Is the SI5335B-B05272-GMR pin-compatible with other Si5335 variants?

Yes, all Si5335 variants - including SI5335B-B05272-GMR - share identical 24-QFN packaging, pinout, and footprint per Skyworks Package Outline document (Section 12). Differences exist only in factory-programmed configuration (frequency plans, output formats, pin functions), not physical layout or electrical pin behavior. This enables drop-in replacement across Si5335 family members during design iteration or volume production, provided the target variant's programmed features meet system requirements.

SI5335B-B05272-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5335B-B05272-GMR FAQ

1.How can I place an order for SI5335B-B05272-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5335B-B05272-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5335B-B05272-GMR reliable?

The price and inventory of SI5335B-B05272-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5335B-B05272-GMR is usually 5 days.

3.What payment methods are accepted for SI5335B-B05272-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5335B-B05272-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5335B-B05272-GMR?

SI5335B-B05272-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5335B-B05272-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5335B-B05272-GMR?

For technical support, including SI5335B-B05272-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5335B-B05272-GMR requirements.

6.How does Aetrix verify that SI5335B-B05272-GMR is sourced from the original manufacturer or authorized distributors?

All SI5335B-B05272-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5335B-B05272-GMR meets industry standards.

7.What is the process for return or replacement of SI5335B-B05272-GMR?

All SI5335B-B05272-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5335B-B05272-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5335B-B05272-GMR part is unused and in its original packaging.

Return procedure for SI5335B-B05272-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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