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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5335B-B05678-GM

Name: SI5335B-B05678-GM
Brand: Skyworks Solutions Inc.
SKU: SI5335B-B05678-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5335B-B05678-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5335B-B05678-GM.pdf

Description:: IC 4OUT ANY FREQ <200MHZ 24QFN

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Product details

Overview

SI5335B-B05678-GM from Skyworks Solutions is a web-customizable, quad-output clock generator supporting four independent non-integer-related frequencies up to 350 MHz, with LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL output formats, 0.7 ps RMS phase jitter, and PCIe Gen 1–4 common-clock compliance - deployed in high-speed serial interconnect timing for FPGA and processor clocking.

For engineers reviewing the SI5335B-B05678-GM datasheet, SI5335B-B05678-GM pinout, SI5335B-B05678-GM application, or SI5335B-B05678-GM equivalent, this device delivers factory-programmed, pin-controlled configuration for PCIe jitter attenuation, DSL timing, broadcast video synchronization, and multi-protocol clock synthesis without external crystals or multiple ICs.

Technical Context

The SI5335B-B05678-GM integrates four independent MultiSynth fractional-N synthesizers fed by a single PLL, enabling simultaneous generation of unrelated output frequencies with zero ppm synthesis error. Its dual-loop bandwidth options (1.6 MHz and 475 kHz) support both PCIe jitter cleanup and DSL spectral noise suppression.

Input flexibility includes differential (LVPECL/LVDS/CML/HCSL, 10–350 MHz), single-ended CMOS (10–200 MHz), or 25/27 MHz crystal reference. Each of the four output banks supports configurable voltage (1.5/1.8/2.5/3.3 V), format, and enable control via five user-assignable pins including SSENB, FS[1:0], RESET, and OEB per bank.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 banks: each supports 1 differential pair or 2 single-ended outputs - enables flexible clock tree distribution across mixed-signal SoCs.
Max output frequency	350 MHz (LVPECL/LVDS/CML/SSTL/HSTL); 250 MHz (HCSL); 200 MHz (CMOS) - covers PCIe Gen4 (100 MHz), 10GbE (156.25 MHz), and Fibre Channel (212.5 MHz).
Phase jitter (RMS)	0.7 ps (12 kHz–20 MHz, 1.6 MHz loop BW) - meets PCIe Gen3 SRNS (≤0.32 ps RMS) and Gen4 (≤0.45 ps RMS) requirements when configured per spec.
Input reference	25/27 MHz crystal, or AC-coupled differential (10–350 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz) - eliminates need for external oscillator in most designs.
Supply & power	Core: 1.8/2.5/3.3 V; I_DDCG = 45 mA (generator mode), I_DB = 12 mA (buffer mode) - enables low-power operation in thermally constrained systems.
Operating temperature	–40 °C to +85 °C - qualified for industrial and telecom line-card environments without derating.
Package	24-pin QFN, 4 mm × 4 mm - compatible with standard SMT reflow and high-density PCB layouts.

Pinout & Package

SI5335B-B05678-GM uses a 24-pin, 4 mm × 4 mm QFN package with exposed thermal pad. Pin functions are fully configurable via ClockBuilder Pro; default assignment aligns with Si5335 family pinout.

Pin/Terminal	Circuit Role	Design Meaning
XA/CLKIN, XB/CLKINB (Pins 1, 2)	Differential input clock or crystal connection	Accepts LVPECL/LVDS/CML/HCSL (10–350 MHz) or 25/27 MHz crystal; internal 18 pF load capacitance enables direct crystal drive.
CLK0A/CLK0B to CLK3A/CLK3B (Pins 3–4, 6–7, 10–11, 13–14)	Differential clock outputs (4 banks)	Each bank independently configurable for LVPECL/LVDS/CML/HCSL; supports 1 differential pair or 2 single-ended signals per bank.
VDDO0–VDDO3 (Pins 5, 8, 12, 15)	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per bank - allows mixed-voltage signaling (e.g., 1.8 V FPGA core + 3.3 V legacy interface).
VDD (Pins 9, 16)	Core logic supply	Single 1.8/2.5/3.3 V rail powers PLL, MultiSynths, and control logic; PSRR optimized for clean clock synthesis.
LOS (Pin 8)	Loss-of-signal alarm output	Open-drain active-low signal asserts within 5 µs of input clock failure - enables system-level fault detection and failover.
P1–P3, P5–P6 (Pins 17–19, 21–22)	Multi-function control inputs	Configurable as SSENB (spread spectrum), FS[1:0] (frequency plan select), RESET, or OEB (output enable) - reduces external GPIO count.

Key Features

Feature	Design Value
MultiSynth fractional-N synthesis	Zero ppm frequency error across all four outputs - eliminates need for multiple crystal oscillators or trimming components.
Three pin-selectable configurations	One device replaces up to three discrete clock generators - simplifies BOM and enables runtime clock plan switching.
PCIe Gen 1–4 common-clock compliance	Validated total jitter ≤33.6 ps pk-pk (Gen1 w/SS) and RMS jitter ≤0.45 ps (Gen3/Gen4) - meets Intel and PCI-SIG timing specifications.
Two selectable PLL loop bandwidths	1.6 MHz (PCIe jitter attenuation) or 475 kHz (DSL spectral shaping) - optimizes phase noise profile for target application.
Flexible output driver configuration	Per-bank voltage (1.5–3.3 V), format (LVPECL to CMOS), and termination - supports heterogeneous system interfaces without level shifters.

Applications

PCI Express Timing	Broadcast Video Synchronization
Use Scenario: Providing synchronized reference clocks to PCIe root complex and endpoint devices in servers and accelerators. IC Role / Device Role / Timing Role: Quad-output clock generator delivering 100 MHz common clock and 125 MHz secondary clocks with sub-0.5 ps RMS jitter. Use Value: Enables PCIe Gen4 link training and stable 16 GT/s data rates while meeting SRNS jitter limits without external jitter cleaners.	Use Scenario: Generating SMPTE-compliant timing signals (e.g., 27 MHz, 74.25 MHz, 148.5 MHz) for HD/4K video encoders and transport streams. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact broadcast frequencies from a single 27 MHz crystal reference. Use Value: Eliminates multiple crystal oscillators and reduces board space by >60% while maintaining <10 ps cycle-cycle jitter for frame-accurate sync.
DSL/MSAN Jitter Attenuation	FPGA & Processor Clocking
Use Scenario: Cleaning noisy DSL line-card reference clocks (e.g., 70.656 MHz) before distribution to ADSL/VDSL PHYs. IC Role / Device Role / Timing Role: Low-bandwidth (475 kHz) PLL-based jitter attenuator with 1.95 ps RMS random jitter (10 Hz–30 MHz). Use Value: Reduces broadband noise-induced bit errors and improves SNR margin in multi-port DSLAMs without analog filters.	Use Scenario: Supplying core, I/O, and transceiver clocks to Xilinx Versal or Intel Agilex FPGAs requiring multiple independent frequencies. IC Role / Device Role / Timing Role: Configurable clock generator synthesizing 500 MHz GTY reference, 300 MHz fabric clock, and 100 MHz PCIe clock simultaneously. Use Value: Replaces 3–4 discrete clock ICs, cuts layout complexity, and enables dynamic reconfiguration via pin-strapped frequency plans.

PCI Express Timing

Broadcast Video Synchronization

Use Scenario: Providing synchronized reference clocks to PCIe root complex and endpoint devices in servers and accelerators.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering 100 MHz common clock and 125 MHz secondary clocks with sub-0.5 ps RMS jitter.

Use Value: Enables PCIe Gen4 link training and stable 16 GT/s data rates while meeting SRNS jitter limits without external jitter cleaners.

Use Scenario: Generating SMPTE-compliant timing signals (e.g., 27 MHz, 74.25 MHz, 148.5 MHz) for HD/4K video encoders and transport streams.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact broadcast frequencies from a single 27 MHz crystal reference.

Use Value: Eliminates multiple crystal oscillators and reduces board space by >60% while maintaining <10 ps cycle-cycle jitter for frame-accurate sync.

DSL/MSAN Jitter Attenuation

FPGA & Processor Clocking

Use Scenario: Cleaning noisy DSL line-card reference clocks (e.g., 70.656 MHz) before distribution to ADSL/VDSL PHYs.

IC Role / Device Role / Timing Role: Low-bandwidth (475 kHz) PLL-based jitter attenuator with 1.95 ps RMS random jitter (10 Hz–30 MHz).

Use Value: Reduces broadband noise-induced bit errors and improves SNR margin in multi-port DSLAMs without analog filters.

Use Scenario: Supplying core, I/O, and transceiver clocks to Xilinx Versal or Intel Agilex FPGAs requiring multiple independent frequencies.

IC Role / Device Role / Timing Role: Configurable clock generator synthesizing 500 MHz GTY reference, 300 MHz fabric clock, and 100 MHz PCIe clock simultaneously.

Use Value: Replaces 3–4 discrete clock ICs, cuts layout complexity, and enables dynamic reconfiguration via pin-strapped frequency plans.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05678-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.5 ps RMS), but larger 32-QFN package and higher cost.	Required for designs needing >4 outputs or ultra-low-jitter SerDes references (e.g., 56G PAM4).	Select if expanding output count or tightening jitter budget beyond SI5335B-B05678-GM's 0.7 ps RMS capability.
ICS8430I-01LG	Fixed-frequency, non-synthesizing quad LVDS buffer; no MultiSynth, no crystal input, no spread spectrum.	Suitable only for simple fanout where input clock matches all required outputs (no frequency translation).	Choose only for cost-sensitive, static-clock-distribution applications without synthesis or jitter attenuation needs.

Compared with Si5332A-D05678-GM and ICS8430I-01LG, the SI5335B-B05678-GM uniquely balances programmability, jitter performance, and footprint - offering web-customized any-frequency synthesis in a compact 24-QFN while remaining pin-compatible with the broader Si5335 family for design reuse.

Availability

SI5335B-B05678-GM is available at Aetrix Electronics and suitable for PCIe Gen4 timing, broadcast video synchronization, DSL jitter attenuation, and FPGA clocking requiring stable component supply, full traceability, and long-term lifecycle support.

Supply support for SI5335B-B05678-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly configurable, low-jitter clock generators targeting high-speed serial interface timing - designed specifically for PCIe, Ethernet, Fibre Channel, and broadcast video systems demanding precise, flexible, and reliable clock synthesis.

FAQ

What is the primary function of the SI5335B-B05678-GM?

The SI5335B-B05678-GM is a quad-output, any-frequency clock generator using Skyworks' MultiSynth fractional-N synthesis to produce four independent, non-integer-related clock signals up to 350 MHz. It replaces multiple oscillators and clock ICs in systems requiring precise, flexible timing - such as PCIe Gen4, 10GbE, and broadcast video equipment - while maintaining 0.7 ps RMS phase jitter and PCIe compliance.

Does the SI5335B-B05678-GM require an external crystal?

The SI5335B-B05678-GM supports both external 25 MHz or 27 MHz crystals (with internal 18 pF load capacitance) and external AC-coupled clock inputs (10–350 MHz differential or 10–200 MHz single-ended). No external crystal is mandatory: it can operate from a system-provided reference clock, making it suitable for clock-buffering and jitter-attenuation roles without added BOM cost.

How many output configurations does the SI5335B-B05678-GM support?

The SI5335B-B05678-GM supports up to three independent, pin-selectable device configurations via FS[1:0] control pins. Each configuration defines unique output frequencies, formats, voltages, and enable states - allowing one physical SI5335B-B05678-GM to serve multiple system modes (e.g., PCIe Gen3 vs. Gen4, or different FPGA clock plans) without firmware update or reprogramming.

What are the supported output voltage levels for the SI5335B-B05678-GM?

The SI5335B-B05678-GM provides independent output buffer supplies (VDDO0–VDDO3) per bank, supporting 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables mixed-voltage clock distribution - for example, driving a 1.8 V FPGA transceiver bank and a 3.3 V legacy peripheral interface simultaneously - without external level shifters or additional regulators.

Is the SI5335B-B05678-GM compliant with PCIe Gen4 timing requirements?

Yes, the SI5335B-B05678-GM is PCIe Gen4 common-clock compliant, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) under specified conditions (100 MHz HCSL outputs, 1.6 MHz loop bandwidth). It meets the PCI-SIG Base Specification 4.0 rev. 0.5 jitter limits for Gen4 links and supports spread-spectrum clocking for EMI reduction in host systems.

SI5335B-B05678-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5335B-B05678-GM FAQ

1.How can I place an order for SI5335B-B05678-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5335B-B05678-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5335B-B05678-GM reliable?

The price and inventory of SI5335B-B05678-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5335B-B05678-GM is usually 5 days.

3.What payment methods are accepted for SI5335B-B05678-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5335B-B05678-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5335B-B05678-GM?

SI5335B-B05678-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5335B-B05678-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5335B-B05678-GM?

For technical support, including SI5335B-B05678-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5335B-B05678-GM requirements.

6.How does Aetrix verify that SI5335B-B05678-GM is sourced from the original manufacturer or authorized distributors?

All SI5335B-B05678-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5335B-B05678-GM meets industry standards.

7.What is the process for return or replacement of SI5335B-B05678-GM?

All SI5335B-B05678-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5335B-B05678-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5335B-B05678-GM part is unused and in its original packaging.

Return procedure for SI5335B-B05678-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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