Skyworks Solutions Inc. SI5335B-B05740-GMR

Overview

SI5335B-B05740-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis, delivering four independent non-integer-related frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and dual selectable PLL loop bandwidths (1.6 MHz / 475 kHz) - deployed in high-speed switch/router timing and FPGA clocking systems.

For engineers reviewing the SI5335B-B05740-GMR datasheet, SI5335B-B05740-GMR pinout, SI5335B-B05740-GMR application, or SI5335B-B05740-GMR equivalent, key selection considerations include differential output format support (LVPECL/LVDS/HCSL/CML), per-output voltage configuration (1.5/1.8/2.5/3.3 V), loss-of-signal alarm, and pin-selectable frequency plan switching for multi-configuration system flexibility.

Technical Context

The SI5335B-B05740-GMR implements a single high-performance PLL with patented MultiSynth fractional-N dividers per output bank, enabling independent synthesis of four output frequencies without integer constraints. It supports both clock generator mode (full synthesis) and buffer mode (PLL bypass), with input reference options including 25/27 MHz crystal, CMOS (10–200 MHz), or differential (10–350 MHz).

Its architecture includes five user-assignable control pins (P1–P3, P5, P6) supporting spread spectrum enable (SSENB), master/output enables (OEB), frequency select (FS[1:0]), and reset. The device features two configurable PLL loop bandwidths optimized for PCIe (1.6 MHz) or DSL (475 kHz) jitter attenuation, and integrated loss-of-signal detection with sub-5 µs response time.

Key Specifications

Pinout & Package

SI5335B-B05740-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5335 family; no variant-specific redefinition is documented for this part number.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-D-GM, SI5335B-B05740-GMR delivers true independent synthesis and PCIe Gen4 compliance; versus LMK04832RHAR, it offers lower power and hardware configurability at the expense of deterministic latency - making it optimal for PCIe, Ethernet, and FPGA clock trees requiring flexibility and low jitter.

Availability

SI5335B-B05740-GMR is available at Aetrix Electronics and suitable for PCIe Gen4 timing, 10GbE switch clocking, and FPGA processor clocking requiring stable component supply, factory-programmed configuration, and long-term industrial temperature support.

Supply support for SI5335B-B05740-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5335 product line was designed as a highly configurable, web-customizable clock generator/buffer platform targeting high-speed digital systems requiring flexible, low-jitter timing with minimal component count - especially in PCIe, Ethernet, and broadcast video applications.

FAQ

What is the primary function of the SI5335B-B05740-GMR?

The SI5335B-B05740-GMR is a quad-output, any-frequency clock generator and buffer IC. It synthesizes four independent, non-integer-related output frequencies up to 350 MHz using Skyworks' MultiSynth fractional-N technology, with 0.7 ps RMS phase jitter and full PCIe Gen 1–4 compliance. Its role is to replace multiple discrete oscillators and clock buffers in high-speed digital systems.

Does the SI5335B-B05740-GMR support PCIe Gen4 timing requirements?

Yes, the SI5335B-B05740-GMR is validated for PCIe Gen4 common clock operation, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) with 1.6 MHz PLL loop bandwidth and 100 MHz HCSL outputs. It meets the PCI-SIG Base Specification 4.0 rev. 0.5 jitter limits without external filtering or reclocking circuitry.

How many independent output voltage rails does the SI5335B-B05740-GMR support?

The SI5335B-B05740-GMR supports four independent output supply rails - VDDO0 through VDDO3 - each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O and 3.3 V legacy peripherals) without external level shifters.

Can the SI5335B-B05740-GMR operate as a pure clock buffer without synthesis?

Yes, the SI5335B-B05740-GMR supports PLL bypass (buffer) mode, where input clock signals pass directly to outputs with only propagation delay (2.5–4 ns). In this mode, core current drops to 12 mA, and the device functions as a low-skew, multi-format clock fanout buffer with configurable output formats and voltages.

What is the purpose of the LOS pin on the SI5335B-B05740-GMR?

The LOS (Loss-of-Signal) pin on the SI5335B-B05740-GMR is an open-drain, active-low indicator that asserts within 5 µs of detecting loss of valid input clock on XA/XB. It provides real-time fault monitoring for redundant clock architectures and enables automatic failover or system alerting without software intervention.