Skyworks Solutions Inc. SI5335C-B04606-GMR

Overview

SI5335C-B04606-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, 0 ppm synthesis error via MultiSynth™ fractional divider technology, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It serves as a single-device replacement for multiple crystal oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335C-B04606-GMR datasheet, SI5335C-B04606-GMR pinout, SI5335C-B04606-GMR application, or SI5335C-B04606-GMR equivalent, key selection criteria include differential/single-ended output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), per-output voltage control (1.5/1.8/2.5/3.3 V), dual PLL loop bandwidth options (475 kHz / 1.6 MHz), loss-of-signal alarm, and pin-selectable frequency plans for multi-configuration system support.

Technical Context

The SI5335C-B04606-GMR implements a single PLL with patented MultiSynth™ fractional-N synthesis driving four independent output banks, each configurable as one differential pair or two single-ended outputs. Input reference supports 25/27 MHz crystals or 10–350 MHz differential/single-ended clocks.

Its architecture enables simultaneous generation of unrelated frequencies with guaranteed 0 ppm frequency error and low-jitter performance optimized for PCIe Gen 3/4 SRNS and DSL jitter attenuation. Two selectable PLL loop bandwidths (475 kHz and 1.6 MHz) allow trade-offs between jitter filtering and lock time in different application domains.

Key Specifications

Pinout & Package

SI5335C-B04606-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5335 family specification and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345A-D-GM and ICS8430I-01LG, SI5335C-B04606-GMR delivers optimal balance of configurability, jitter performance (0.7 ps RMS), and compact 24-QFN packaging for mid-range PCIe Gen 3/4, Ethernet, and FPGA timing-supporting both generator and buffer modes without requiring layout redesign or additional components.

Availability

SI5335C-B04606-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE telecom switches, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and factory-programmable timing solutions.

Supply support for SI5335C-B04606-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line was designed to replace multiple discrete clock sources with a single, field-programmable, any-frequency clock generator for high-speed serial interface timing in datacenter, networking, and broadcast infrastructure.

FAQ

What is the primary function of the SI5335C-B04606-GMR in a PCIe Gen 4 system?

The SI5335C-B04606-GMR serves as a common clock source delivering 100 MHz HCSL clocks compliant with PCIe Gen 4 jitter requirements (0.15–0.45 ps RMS). Its dual-loop bandwidth (475 kHz / 1.6 MHz) and SRNS mode enable it to meet strict phase noise masks without external jitter cleaners, directly replacing multiple oscillators in root complex and endpoint timing paths.

Does the SI5335C-B04606-GMR support crystal oscillator input?

Yes, the SI5335C-B04606-GMR supports on-chip 25 MHz or 27 MHz crystal connections via pins 1 and 2 (XA/CLKIN and XB/CLKINB). The internal crystal driver provides 18 pF load capacitance, supports ESR ≤ 100 Ω, and requires no external load capacitors-enabling a complete, self-contained clock solution without external crystal circuitry.

How many independent output voltage supplies does the SI5335C-B04606-GMR support?

The SI5335C-B04606-GMR supports four independent output buffer supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous interfacing with mixed-voltage devices-such as 1.8 V FPGAs, 2.5 V SerDes, and 3.3 V legacy peripherals-without external level translators or LDOs.

Can the SI5335C-B04606-GMR operate in clock buffer mode?

Yes, the SI5335C-B04606-GMR supports PLL bypass (buffer) mode, where input clock signals pass through with minimal added jitter (2.5–4 ns propagation delay). In this mode, core current drops to 12 mA, and the device functions as a low-skew, multi-format fanout buffer supporting frequencies from 5 MHz to 350 MHz depending on input format.

What is the purpose of the LOS pin on the SI5335C-B04606-GMR?

The LOS (Loss of Signal) pin on the SI5335C-B04606-GMR is an open-drain output that asserts low within 2.6–5 µs of detecting absence of a valid input clock on XA/XB pins. It enables real-time system monitoring and failover triggering in mission-critical applications such as telecom line cards and broadcast infrastructure where clock redundancy is essential.