Skyworks Solutions Inc. SI5335C-B04623-GMR

Overview

SI5335C-B04623-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis, delivering four independent non-integer-related frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and configurable LVPECL/LVDS/HCSL/CMOS/SSTL outputs - used in high-speed serial interface timing for Ethernet switches and PCIe root complexes.

For engineers reviewing the SI5335C-B04623-GMR datasheet, SI5335C-B04623-GMR pinout, SI5335C-B04623-GMR application, or SI5335C-B04623-GMR equivalent, key selection criteria include differential output jitter performance at 100 MHz HCSL, dual PLL loop bandwidth (475 kHz / 1.6 MHz), loss-of-signal alarm functionality, and pin-selectable frequency plan switching across three user-defined configurations.

Technical Context

The SI5335C-B04623-GMR implements a single PLL with patented MultiSynth fractional divider architecture per output bank, enabling independent synthesis of four output frequencies without integer constraints. It supports both clock generator mode (PLL active) and low-jitter clock buffer mode (PLL bypass), with input reference options including 25/27 MHz crystal, CMOS (10–200 MHz), or differential (10–350 MHz).

Its control architecture includes five multi-function pins (P1–P6) assignable to spread spectrum enable (SSENB), master/output enables (OEB), frequency select (FS1/FS0), or reset. The device integrates loss-of-signal detection on CLKIN inputs with sub-5 µs response time and supports PCIe SRNS compliance via selectable loop bandwidth and jitter filtering.

Key Specifications

Pinout & Package

SI5335C-B04623-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad (RoHS-compliant, lead-free). Pin assignments follow standard Si5335 top-view layout with dedicated input (XA/CLKIN, XB/CLKINB), output (CLK0A–CLK3B), supply (VDD, VDDO0–VDDO3), control (P1–P6), and status (LOS) terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-D-GM and ICS8430I-01T, SI5335C-B04623-GMR uniquely combines any-frequency synthesis, PCIe Gen 4 compliance, loss-of-signal monitoring, and three-pin-selectable configurations - making it the only option for reconfigurable, high-speed serial timing in next-generation infrastructure platforms.

Availability

SI5335C-B04623-GMR is available at Aetrix Electronics and suitable for PCIe root complex timing, Ethernet switch synchronization, broadcast video frame locking, and telecom line card clocking requiring stable component supply and long-term industrial temperature support.

Supply support for SI5335C-B04623-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5335 product line delivers web-customizable, multi-output clock generators targeting high-speed serial interface timing in datacenter, telecom, and broadcast equipment - designed to replace discrete clock trees with single-chip programmable precision.

FAQ

What is the primary function of the SI5335C-B04623-GMR in a PCIe Gen 4 system?

The SI5335C-B04623-GMR serves as a common clock generator delivering four precisely timed reference clocks to PCIe Gen 4 endpoints and root ports. It achieves ≤0.45 ps RMS jitter at 100 MHz using its 1.6 MHz PLL loop bandwidth and MultiSynth synthesis, meeting PCI-SIG specification requirements without external jitter cleaners or additional buffering stages.

Does the SI5335C-B04623-GMR require an external crystal, and what frequencies are supported?

Yes, the SI5335C-B04623-GMR supports external 25 MHz or 27 MHz crystals connected to XA/CLKIN and XB/CLKINB pins. Internal load capacitance is fixed at 18 pF, and crystal ESR must be ≤100 Ω (25 MHz) or ≤75 Ω (27 MHz). It also accepts CMOS, SSTL, HSTL, or differential clock inputs from 10 MHz to 350 MHz.

How many independent frequency plans can be stored and selected on the SI5335C-B04623-GMR?

The SI5335C-B04623-GMR supports three independent, factory-programmed frequency configurations. These are selected in real time using the FS1 and FS0 control pins (P5 and P6), enabling dynamic switching between distinct clocking schemes - for example, toggling between PCIe Gen 3 and Gen 4 modes or between different Ethernet PHY rates.

What output formats and voltage levels does the SI5335C-B04623-GMR support per bank?

Each of the four output banks on the SI5335C-B04623-GMR supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL formats. Independent VDDO supplies (VDDO0–VDDO3) allow per-bank voltage selection from 1.5 V, 1.8 V, 2.5 V, or 3.3 V - enabling direct interfacing with mixed-voltage FPGAs, ASICs, and PHYs without level-shifting components.

Is the SI5335C-B04623-GMR compatible with PCIe SRNS (Separate Reference No Spread) requirements?

Yes, the SI5335C-B04623-GMR is PCIe Gen 3 SRNS compliant, achieving ≤0.32 ps RMS jitter under SRNS test conditions (2–5 MHz PLL bandwidth, 10 MHz CDR). This capability is enabled by its selectable loop bandwidth and internal jitter filtering architecture, validated per PCI-SIG specifications using the Skyworks PCIe Clock Jitter Tool.