Skyworks Solutions Inc. SI5335D-B04175-GMR

Overview

SI5335D-B04175-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC supporting four independent, non-integer-related frequencies up to 350 MHz. It features MultiSynth fractional synthesis with 0 ppm frequency error, PCIe Gen 1–4 common clock compliance, and dual selectable PLL loop bandwidths (1.6 MHz / 475 kHz). Used in high-speed serial interface timing for PCIe root complexes and Ethernet switch fabric.

For engineers reviewing the SI5335D-B04175-GMR datasheet, SI5335D-B04175-GMR pinout, SI5335D-B04175-GMR application, or SI5335D-B04175-GMR equivalent, key selection criteria include differential output jitter (0.7 ps RMS), flexible input support (25/27 MHz crystal or 10–350 MHz differential/CMOS), per-output voltage control (1.5/1.8/2.5/3.3 V), and factory-configurable pin-selectable device configurations.

Technical Context

The SI5335D-B04175-GMR implements a single PLL with four independent MultiSynth fractional dividers, enabling simultaneous synthesis of unrelated output frequencies without integer constraints. Each output bank supports configurable format (LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL) and voltage (1.5–3.3 V).

It accepts multiple reference inputs: 25 or 27 MHz crystal (on-chip load capacitance 18 pF), or AC-coupled differential (10–350 MHz) or single-ended (10–200 MHz) clocks. Loss-of-signal detection (2.6–5 µs response) and five user-assignable control pins (P1–P6) support spread spectrum enable, reset, OEB, and frequency plan selection.

Key Specifications

Pinout & Package

SI5335D-B04175-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow the standard Si5335 top-view layout, including dual differential inputs (XA/CLKIN, XB/CLKINB), four differential output pairs (CLK0A/B through CLK3A/B), three dedicated control pins (P1, P2, P3), two multi-function pins (P5, P6), loss-of-signal indicator (LOS), and eight power/ground terminals (VDD, VDDO0–VDDO3, GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-D-GM and ICS8430I-01LG, the SI5335D-B04175-GMR uniquely balances 4-output flexibility, 0 ppm synthesis, PCIe Gen 4 compliance, and compact 24-QFN packaging-making it optimal for space-constrained, multi-protocol timing in compute and networking platforms.

Availability

SI5335D-B04175-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, 10G/25G Ethernet switch fabric, and telecom line card applications requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.

Supply support for SI5335D-B04175-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and SONET-enabling system-level timing consolidation and jitter compliance without external components.

FAQ

What is the primary function of the SI5335D-B04175-GMR?

The SI5335D-B04175-GMR is a quad-output, any-frequency clock generator/buffer IC. Its primary function is to synthesize up to four independent, non-integer-related output frequencies (1–350 MHz) from a single reference input (25/27 MHz crystal or 10–350 MHz clock) using Skyworks' MultiSynth fractional divider technology. It delivers 0 ppm frequency error and supports PCIe Gen 1–4, Ethernet, and telecom timing standards. The SI5335D-B04175-GMR replaces multiple discrete oscillators and clock ICs in high-speed digital systems.

Does the SI5335D-B04175-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04175-GMR is PCIe Gen 4 common clock compliant. In clock generator mode with 1.6 MHz PLL loop bandwidth, it achieves ≤0.45 ps RMS jitter (12 kHz–20 MHz) on 100 MHz HCSL outputs-meeting the PCIe Gen 4 Base Specification 4.0 requirement. It also supports SRNS mode for separate-reference applications. Validation uses the Intel Clock Jitter Tool and Skyworks' PCIe Clock Jitter Tool, and the SI5335D-B04175-GMR is explicitly listed in Skyworks' PCIe Gen 4 compliance documentation.

Can the SI5335D-B04175-GMR operate as a pure clock buffer?

Yes, the SI5335D-B04175-GMR supports PLL bypass mode, functioning as a configurable universal buffer and level translator. In this mode, it passes the input reference directly to outputs with <4 ns propagation delay, 12 mA core current draw, and full output format/voltage configurability (LVPECL/LVDS/CMOS/etc.). The SI5335D-B04175-GMR retains all pin-selectable controls-including individual output enables and spread spectrum-even in buffer mode, making it suitable for jitter-sensitive fanout applications.

How many device configurations can be stored and selected on the SI5335D-B04175-GMR?

The SI5335D-B04175-GMR supports up to three independent, factory-programmed, pin-selectable device configurations. These are selected via the FS1 and FS0 control pins (P5 and P6), allowing hardware-based switching between distinct frequency plans, output formats, and voltage settings without I²C reprogramming. This capability enables one SI5335D-B04175-GMR to replace three separate clock generators in systems requiring field-upgradable or mode-dependent timing schemes.

What package type and thermal considerations apply to the SI5335D-B04175-GMR?

The SI5335D-B04175-GMR uses a 4 mm × 4 mm, 24-pin QFN package with an exposed thermal pad. The pad must be soldered to a solid copper thermal plane on the PCB for reliable operation across –40 °C to +85 °C. Decoupling capacitors (0.1 µF ceramic + 1–10 µF bulk) are required per VDD and VDDO rail, placed adjacent to respective pins. Thermal resistance (θ_JA) is 35 °C/W typical; junction temperature must remain below 125 °C under worst-case 45 mA core current. The SI5335D-B04175-GMR datasheet specifies land pattern and solder stencil guidelines in Section 13.