Skyworks Solutions Inc. SI5335D-B04203-GMR

Overview

SI5335D-B04203-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with four independent MultiSynth fractional dividers, synthesizing non-integer-related frequencies up to 350 MHz. It supports LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL outputs, features 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and operates across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces multiple oscillators and clock ICs in high-speed serial interface timing.

For engineers reviewing the SI5335D-B04203-GMR datasheet, SI5335D-B04203-GMR pinout, SI5335D-B04203-GMR application, or SI5335D-B04203-GMR equivalent, key selection considerations include its 0 ppm frequency synthesis error, dual PLL loop bandwidth options (1.6 MHz / 475 kHz), loss-of-signal alarm, five user-assignable control pins, and factory-configurable output formats via ClockBuilder Pro.

Technical Context

The SI5335D-B04203-GMR implements Skyworks' patented MultiSynth fractional-N synthesis architecture per output bank, enabling independent, any-frequency generation without integer constraints. Each of its four output banks supports either one differential pair or two single-ended signals, with programmable voltage per driver (1.5/1.8/2.5/3.3 V) and format-selectable drivers (LVPECL, LVDS, CML, HCSL, CMOS, SSTL, HSTL).

It accepts flexible input references: 25/27 MHz crystal, or AC-coupled CMOS/SSTL/HSTL/differential clocks from 10–350 MHz. Two selectable PLL loop bandwidths (1.6 MHz for PCIe jitter attenuation; 475 kHz for DSL applications) and integrated loss-of-signal detection support robust system-level timing integrity in jitter-sensitive serial links.

Key Specifications

Pinout & Package

SI5335D-B04203-GMR is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are fixed per the Si5335 family; no variant-specific redefinition is documented for this part number.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5341-B-GM and ICS8430I-01T, SI5335D-B04203-GMR uniquely balances field-programmable frequency agility, PCIe Gen4 readiness, and compact 24-QFN packaging - making it optimal for next-generation embedded computing and networking platforms requiring rapid customization and multi-standard support.

Availability

SI5335D-B04203-GMR is available at Aetrix Electronics and suitable for PCIe Gen4 timing, 10GbE switch clocking, and FPGA-based video processing applications requiring stable component supply, factory-programmed configuration, and long-term industrial temperature support.

Supply support for SI5335D-B04203-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly configurable, web-customized clock generators targeting high-speed serial interface timing in PCIe, Ethernet, Fibre Channel, and broadcast video systems - emphasizing synthesis accuracy, low jitter, and design flexibility.

FAQ

What is the primary function of the SI5335D-B04203-GMR in a PCIe Gen4 system?

The SI5335D-B04203-GMR serves as a quad-output common clock generator in PCIe Gen4 systems, delivering up to four independent, low-jitter reference clocks (e.g., 100 MHz) with <0.45 ps RMS jitter and PCIe Gen4 common clock compliance. Its 1.6 MHz PLL bandwidth and spread spectrum control meet stringent jitter requirements while replacing multiple discrete oscillators - directly improving signal integrity and reducing board area in host CPU and accelerator designs.

Does the SI5335D-B04203-GMR support crystal input, and what frequencies are validated?

Yes, the SI5335D-B04203-GMR supports on-chip crystal oscillator circuitry for 25 MHz and 27 MHz fundamental-mode crystals, with internal 18 pF load capacitance and ESR limits of 100 Ω (25 MHz) or 75 Ω (27 MHz). The device does not support other crystal frequencies; external AC-coupled clock inputs (10–350 MHz) are required for non-standard references.

How many independent output voltage rails does the SI5335D-B04203-GMR support, and why does that matter?

The SI5335D-B04203-GMR supports four independent output buffer supply rails (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct level translation to mixed-voltage receivers - such as 1.8 V FPGA I/O banks, 2.5 V SerDes, and 3.3 V legacy peripherals - without external level shifters, simplifying routing and preserving signal integrity across diverse interface standards.

Can the SI5335D-B04203-GMR operate in clock buffer mode, and what are its key characteristics in that mode?

Yes, the SI5335D-B04203-GMR supports PLL bypass (buffer) mode with 12 mA typical core current, 2.5–4 ns input-to-output propagation delay, and operation down to 1 MHz input frequency (though LOS detection is disabled below 5 MHz). In this mode, it functions as a low-skew (<100 ps), format-flexible (LVPECL/LVDS/HCSL/CMOS) fanout buffer - ideal for distributing a clean master clock without frequency translation.

What control pin functions are supported by the SI5335D-B04203-GMR, and how are they assigned?

The SI5335D-B04203-GMR provides five user-assignable control pins (P1, P2, P3, P5, P6) supporting SSENB (spread spectrum enable), RESET, master or individual output enable (OEB_all/OEB_n), and frequency plan selection (FS[1:0]). Assignment is defined during factory configuration via ClockBuilder Pro; no runtime reprogramming is possible - ensuring deterministic behavior and eliminating firmware dependencies in safety-critical timing paths.