Skyworks Solutions Inc. SI5335D-B04218-GMR

Overview

SI5335D-B04218-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis, delivering four independent, non-integer-related frequencies up to 350 MHz. It supports LVPECL/LVDS/HCSL/CMOS/SSTL outputs, features 0.7 ps RMS phase jitter, dual selectable PLL loop bandwidths (475 kHz / 1.6 MHz), and operates from –40 to +85 °C in a 4 × 4 mm 24-QFN package - used in PCIe Gen 4 common-clock systems and Ethernet switch timing.

For engineers reviewing the SI5335D-B04218-GMR datasheet, SI5335D-B04218-GMR pinout, SI5335D-B04218-GMR application, or SI5335D-B04218-GMR equivalent, key selection considerations include PCIe Gen 3/4 SRNS compliance, loss-of-signal alarm capability, pin-selectable frequency plans, spread spectrum control via SSENB, and independent output voltage per driver (1.5/1.8/2.5/3.3 V).

Technical Context

The SI5335D-B04218-GMR integrates a high-performance PLL with patented MultiSynth fractional divider technology, enabling zero-ppm frequency synthesis error across all four output banks. Each bank supports either one differential pair or two single-ended outputs, with independent format (LVPECL, LVDS, CML, HCSL, CMOS, SSTL, HSTL) and voltage (1.5–3.3 V) configuration.

It accepts multiple reference inputs: 25/27 MHz crystal, or AC-coupled CMOS/SSTL/HSTL/differential signals from 10–350 MHz. Two configurable PLL loop bandwidths (475 kHz for DSL jitter attenuation; 1.6 MHz for PCIe) and five user-assignable control pins (P1–P3, P5, P6) support PCIe-compliant spread spectrum, master/output enables, frequency plan selection, and reset.

Key Specifications

Pinout & Package

SI5335D-B04218-GMR uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Rev. 1.4 datasheet: Pins 1–2 = XA/CLKIN & XB/CLKINB; Pins 3–4 = CLK2B & CLK2A; Pins 5–6 = VDDO2 & VDDO1; Pins 7–8 = CLK1B & CLK1A; Pins 9–10 = VDD & VDD; Pins 11–12 = CLK3A & CLK3B; Pin 13 = LOS; Pins 14–15 = VDDO0 & CLK0B; Pins 16–17 = CLK0A & RSVD_GND; Pins 18–24 = VDDO3, GND, GND, Pad, P1, P2, P3, P5, P6.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345B-D08589-GM and ICS853S01AGI-01LFT, SI5335D-B04218-GMR uniquely balances quad-output synthesis, PCIe Gen 4 compliance, pin-selectable configurations, and loss-of-signal detection - making it the most versatile choice for mid-tier communications and computing platforms requiring both flexibility and reliability.

Availability

SI5335D-B04218-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switch fabric timing, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and factory-programmed configurations.

Supply support for SI5335D-B04218-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5335 product line was designed as a highly configurable, web-customizable clock generator family targeting high-speed digital systems requiring precise, flexible, and reliable timing - especially PCIe, Ethernet, and telecom applications where jitter, configurability, and footprint matter.

FAQ

What is the maximum output frequency supported by the SI5335D-B04218-GMR?

The SI5335D-B04218-GMR supports up to 350 MHz on LVPECL, LVDS, CML, SSTL, and HSTL outputs; 250 MHz on HCSL; and 200 MHz on CMOS outputs. These limits are validated across all operating conditions (–40 to +85 °C, 1.8/2.5/3.3 V supplies) and apply regardless of input reference source - crystal, CMOS, or differential. The device maintains 0 ppm synthesis error at all supported frequencies due to its MultiSynth architecture.

Does the SI5335D-B04218-GMR support PCIe Gen 4 common clock compliance?

Yes, the SI5335D-B04218-GMR is explicitly specified for PCIe Gen 4 common clock compliance, achieving ≤0.45 ps RMS jitter (12 kHz–20 MHz) at 100 MHz output with 1.6 MHz PLL loop bandwidth. It meets the PCI-SIG Base Specification 4.0 rev. 0.5 requirements when configured per Skyworks' recommended settings - including spread spectrum disabled and HCSL output format. Validation data is provided in Table 8 of the Rev. 1.4 datasheet.

How many independent output voltage rails does the SI5335D-B04218-GMR support?

The SI5335D-B04218-GMR supports four independent output voltage rails (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous generation of mixed-voltage clocks - for example, 1.8 V for an FPGA core and 3.3 V for a legacy peripheral interface - without external level shifters. Voltage selection is set per rail during factory programming via ClockBuilder Pro.

Can the SI5335D-B04218-GMR operate as a pure clock buffer without PLL synthesis?

Yes, the SI5335D-B04218-GMR supports PLL bypass mode (buffer mode), where input clocks pass through with minimal latency (2.5–4 ns propagation delay) and no frequency translation. In this mode, core supply current drops to 12 mA, and minimum input frequency is 5 MHz (1 MHz supported but without LOS functionality). Buffer mode retains all output formatting, voltage control, and pin-selectable features - making it ideal for low-power fanout applications.

What is the function of the LOS pin on the SI5335D-B04218-GMR?

The LOS (Loss-of-Signal) pin (Pin 13) is an open-drain output that asserts low within 5 µs of detecting failure on the primary reference input (XA/XB). It deasserts within 1 µs after signal recovery. This fast-response alarm enables real-time system fault detection, automatic switchover to backup clocks, and logging of timing failures - critical for telecom and industrial applications requiring high availability. LOS status is monitored internally and requires no external components.