Skyworks Solutions Inc. SI5335D-B04331-GM

Overview

SI5335D-B04331-GM from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC supporting four independent non-integer-related frequencies up to 350 MHz. It features MultiSynth fractional divider technology with 0 ppm synthesis error, PCIe Gen 1–4 common clock compliance, and dual selectable PLL loop bandwidths (1.6 MHz / 475 kHz). It serves as a single-chip replacement for multiple oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335D-B04331-GM datasheet, SI5335D-B04331-GM pinout, SI5335D-B04331-GM application, or SI5335D-B04331-GM equivalent, key selection considerations include its 0.7 ps RMS phase jitter, flexible output format support (LVPECL/LVDS/HCSL/CMOS/SSTL), loss-of-signal alarm, and five user-assignable control pins for spread spectrum, reset, and frequency plan selection.

Technical Context

The SI5335D-B04331-GM integrates a single high-performance PLL with four independent MultiSynth fractional dividers, enabling simultaneous synthesis of four unrelated output frequencies. Its architecture supports both clock generator mode (with PLL active) and low-jitter clock buffer mode (PLL bypass), delivering 2.5 ns input-to-output propagation delay in buffer mode.

It accepts multiple reference inputs - 25/27 MHz crystal, or AC-coupled CMOS/SSTL/HSTL/differential signals from 10–350 MHz - and provides per-output voltage selection (1.5/1.8/2.5/3.3 V) and format configuration. The device implements loss-of-signal detection with 2.6–5 µs response time and supports PCIe SRNS compliance via configurable loop bandwidth.

Key Specifications

Pinout & Package

SI5335D-B04331-GM is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are fixed per the Si5335 family layout and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5332D-A05331-GM and ICS8430I-01LG, the SI5335D-B04331-GM uniquely balances field-programmable frequency synthesis, PCIe compliance, and compact 24-QFN packaging-making it optimal for space-constrained, multi-protocol systems requiring hardware-configurable timing without firmware dependency.

Availability

SI5335D-B04331-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switch fabric timing, and telecom line card jitter attenuation requiring stable component supply and long-term lifecycle support.

Supply support for SI5335D-B04331-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly configurable, any-frequency clock generation for high-speed serial interfaces-including PCIe, Ethernet, and telecom standards-enabling consolidation of multiple timing components into a single programmable IC.

FAQ

What is the primary function of the SI5335D-B04331-GM?

The SI5335D-B04331-GM is a quad-output, web-customizable clock generator/buffer IC that synthesizes up to four independent, non-integer-related frequencies (1–350 MHz) with 0 ppm frequency error. It operates in either PLL-based clock generation mode or low-latency PLL-bypass buffer mode, and is specifically designed for PCIe Gen 1–4, 10 GbE, and telecom timing applications. Its MultiSynth architecture ensures deterministic jitter performance across all configurations.

Does the SI5335D-B04331-GM support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04331-GM meets PCIe Gen 4 common clock jitter specifications with ≤0.45 ps RMS (12 kHz–20 MHz) when configured with 1.6 MHz PLL loop bandwidth and HCSL outputs. It is explicitly validated for PCIe Gen 4 in the official datasheet (Rev. 1.4, Table 8), and supports spread spectrum modulation for EMI compliance. The SI5335D-B04331-GM also satisfies Gen 3 SRNS requirements with ≤0.32 ps RMS jitter under specified test conditions.

How many independent output voltage supplies does the SI5335D-B04331-GM support?

The SI5335D-B04331-GM supports four independent output buffer supply rails (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous interfacing with mixed-voltage logic families-such as 1.8 V FPGAs, 2.5 V ASICs, and 3.3 V legacy peripherals-without external level shifters. Each rail powers one of the four output banks, ensuring noise isolation between domains.

Can the SI5335D-B04331-GM operate without an external crystal?

Yes, the SI5335D-B04331-GM can operate without an external crystal by accepting an external AC-coupled clock signal (10–350 MHz) on XA/CLKIN and XB/CLKINB pins. It supports CMOS, SSTL, HSTL, and differential input formats. While a 25 or 27 MHz crystal is optional for standalone operation, the device is fully functional with a system-provided reference, making it suitable for backplane-synchronized or daisy-chained timing architectures.

What is the purpose of the LOS pin on the SI5335D-B04331-GM?

LOS (Loss-of-Signal) is an open-drain output pin (Pin 8) that asserts low within 2.6–5 µs of detecting failure on the primary reference input (XA/XB). It provides hardware-level fault indication for system monitoring and failover circuits-enabling immediate switchover to backup clocks or safe shutdown sequences. The SI5335D-B04331-GM's LOS functionality is active in both PLL and buffer modes and requires an external pull-up resistor per the datasheet layout guidelines.