Skyworks Solutions Inc. SI5335D-B04331-GMR

Overview

SI5335D-B04331-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC synthesizing four non-integer-related output frequencies up to 350 MHz using MultiSynth fractional divider technology. It delivers 0 ppm frequency synthesis error, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates across –40 to +85 °C with 1.8/2.5/3.3 V core supply. It serves in high-speed serial interface timing for Ethernet switches and FPGA clocking.

For engineers reviewing the SI5335D-B04331-GMR datasheet, SI5335D-B04331-GMR pinout, SI5335D-B04331-GMR application, or SI5335D-B04331-GMR equivalent, key selection considerations include its dual PLL loop bandwidth (475 kHz / 1.6 MHz), 0.7 ps RMS phase jitter, flexible output format support (LVPECL/LVDS/HCSL/CMOS/SSTL), loss-of-signal alarm, and five user-assignable control pins for spread spectrum, reset, and frequency plan selection.

Technical Context

The SI5335D-B04331-GMR implements a single PLL architecture with four independent MultiSynth fractional dividers per output bank, enabling any-frequency synthesis without integer constraints. Its input accepts 10–350 MHz differential (LVDS/LVPECL/CML/HSTL) or 10–200 MHz single-ended (CMOS/SSTL/HSTL) references, or a 25/27 MHz crystal.

Each of the four output banks supports either one differential pair or two single-ended outputs, with independently configurable voltage (1.5/1.8/2.5/3.3 V), format, and enable control. The device supports both clock generator mode (45 mA core current) and low-power buffer mode (12 mA core current) with PLL bypass.

Key Specifications

Pinout & Package

SI5335D-B04331-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5335 pinout: dual differential inputs (XA/CLKIN, XB/CLKINB), four differential output pairs (CLK0A/B through CLK3A/B), three multi-function control pins (P1, P2, P3), two additional programmable pins (P5, P6), loss-of-signal indicator (LOS), power (VDD, VDDO0–VDDO3), and ground (GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345B-D08689-GM and ICS8430I-01T, the SI5335D-B04331-GMR offers optimal balance of web-customizable synthesis, PCIe Gen 4 readiness, and industrial temperature operation in a proven 24-QFN package - making it ideal for mid-tier telecom and networking designs where configurability and validation maturity outweigh ultra-low jitter or EEPROM convenience.

Availability

SI5335D-B04331-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 timing, and broadcast video/audio timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5335D-B04331-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5335 product line was designed as a highly configurable, web-customizable clock generator/buffer family targeting high-speed serial interface timing in networking, computing, and communications equipment - emphasizing jitter performance, multi-protocol compliance, and design flexibility.

FAQ

What is the primary function of the SI5335D-B04331-GMR?

The SI5335D-B04331-GMR is a quad-output, web-customizable clock generator/buffer IC that synthesizes four independent, non-integer-related frequencies up to 350 MHz with 0 ppm frequency error. It serves as a timing solution for PCIe, Ethernet, FPGA, and telecom applications - functioning either as a precision frequency synthesizer or a low-jitter buffer with PLL bypass capability.

Does the SI5335D-B04331-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04331-GMR meets PCIe Gen 4 common clock jitter specifications (≤0.45 ps RMS, 12 kHz–20 MHz) when configured with 1.6 MHz PLL loop bandwidth and differential outputs (e.g., HCSL). It is validated per PCI-SIG requirements using the Intel Clock Jitter Tool and supports both common clock and SRNS topologies.

How many output formats does the SI5335D-B04331-GMR support, and can they be mixed?

The SI5335D-B04331-GMR supports LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL output formats - with independent configuration per output bank. Mixed formats are fully supported: for example, CLK0A/B as LVDS, CLK1A/B as HCSL, CLK2A/B as CMOS, and CLK3A/B as SSTL - each with its own VDDO voltage setting.

What is the role of the LOS pin on the SI5335D-B04331-GMR?

The LOS (Loss-of-Signal) pin on the SI5335D-B04331-GMR is an open-drain indicator that asserts low within 5 µs of detecting failure on the primary reference input (XA/XB). It enables real-time monitoring of clock source health and can trigger system-level failover or diagnostic routines without requiring host processor intervention.

Can the SI5335D-B04331-GMR operate without an external crystal?

Yes, the SI5335D-B04331-GMR can operate without an external crystal by accepting an external AC-coupled differential (10–350 MHz) or single-ended (10–200 MHz) clock on XA/XB or CLKIN pins. However, if using the internal crystal oscillator, a 25 MHz or 27 MHz fundamental-mode crystal must be connected to XA/XB - no other frequencies are supported for crystal mode.