Skyworks Solutions Inc. SI5335D-B04333-GMR

Overview

SI5335D-B04333-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis, delivering four independent non-integer-related frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and configurable LVPECL/LVDS/HCSL/CMOS/SSTL outputs - used in high-speed serial interface timing for Ethernet switches and PCIe root complexes.

For engineers reviewing the SI5335D-B04333-GMR datasheet, SI5335D-B04333-GMR pinout, SI5335D-B04333-GMR application, or SI5335D-B04333-GMR equivalent, key selection criteria include its dual-loop-bandwidth (1.6 MHz / 475 kHz) PLL architecture, loss-of-signal alarm, five user-assignable control pins (P1–P6), and factory-programmable configuration via ClockBuilder Pro - critical for jitter-sensitive PCIe Gen 4 and DSL systems.

Technical Context

The SI5335D-B04333-GMR implements a single PLL with two selectable loop bandwidths (1.6 MHz for PCIe jitter attenuation, 475 kHz for DSL applications) and four independent MultiSynth fractional dividers - each driving one differential pair or two single-ended outputs. It supports pin-selectable device configurations (up to three), enabling dynamic frequency plan switching without reprogramming.

Input flexibility includes crystal (25/27 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references; output voltage per bank is independently set to 1.5/1.8/2.5/3.3 V, and driver formats are fully configurable per bank - LVPECL (1–350 MHz), HCSL (1–250 MHz), CMOS (1–200 MHz), or SSTL/HSTL (1–350 MHz).

Key Specifications

Pinout & Package

SI5335D-B04333-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet (pages 2, 38–40), including dual differential inputs (XA/CLKIN, XB/CLKINB), four differential clock output banks (CLK0A/B through CLK3A/B), loss-of-signal indicator (LOS), six multi-function control pins (P1–P6), and dedicated VDD/VDDO/GND terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-D-GM and ICS8430I-01LG, SI5335D-B04333-GMR uniquely combines differential reference support, PCIe Gen 4–compliant jitter, and field-programmable MultiSynth synthesis - enabling single-device replacement of multiple fixed-clock ICs in multi-protocol infrastructure equipment.

Availability

SI5335D-B04333-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, 10 GbE switch clocking, and DSLAM jitter attenuation requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5335D-B04333-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 family is designed as a highly configurable, web-customizable clock generator platform targeting high-speed serial interface timing - specifically engineered to consolidate multiple clock sources into a single IC for PCIe, Ethernet, and telecom infrastructure.

FAQ

What is the primary function of the SI5335D-B04333-GMR?

The SI5335D-B04333-GMR is a quad-output, any-frequency clock generator/buffer IC that synthesizes four independent, non-integer-related clock signals up to 350 MHz using Skyworks' MultiSynth fractional divider technology. It serves as a timing solution for PCIe Gen 4, 10 GbE, and DSL systems - replacing multiple discrete oscillators and clock ICs with a single programmable device.

Does the SI5335D-B04333-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04333-GMR meets PCIe Gen 4 common clock jitter specifications (≤0.45 ps RMS, 12 kHz–20 MHz) when configured with the 1.6 MHz PLL loop bandwidth and differential outputs. Its 0.7 ps RMS typical phase jitter and PCIe Gen 1–4 compliance are validated per Skyworks Rev. 1.4 datasheet Table 8 and AN562 test methodology.

How many independent output voltage supplies does the SI5335D-B04333-GMR support?

The SI5335D-B04333-GMR supports four independent output buffer supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous interfacing with mixed-voltage components - for example, driving a 1.8 V FPGA bank and a 3.3 V legacy peripheral from the same IC without external level shifters.

Can the SI5335D-B04333-GMR operate without an external crystal?

Yes, the SI5335D-B04333-GMR accepts multiple reference inputs: external 25/27 MHz crystals, single-ended CMOS (10–200 MHz), or differential (10–350 MHz) clocks on XA/CLKIN and XB/CLKINB. Crystal operation is optional - the device functions fully with an external clock source, making it suitable for systems where crystal placement is constrained.

What is the role of the LOS pin on the SI5335D-B04333-GMR?

The LOS (Loss-of-Signal) pin on the SI5335D-B04333-GMR is an open-drain, active-low output that asserts within 2.6–5 µs of input clock failure. It provides real-time monitoring of reference clock integrity - enabling system-level fault detection, failover triggering, or safe shutdown sequences in telecom and industrial applications where clock reliability is mission-critical.