Skyworks Solutions Inc. SI5335D-B04375-GMR

Overview

SI5335D-B04375-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, 0 ppm synthesis error via MultiSynth™ fractional divider technology, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL outputs in a 4×4 mm 24-QFN package. It serves as a single-device replacement for multiple clock ICs and crystal oscillators in high-speed serial interface timing systems.

For engineers reviewing the SI5335D-B04375-GMR datasheet, SI5335D-B04375-GMR pinout, SI5335D-B04375-GMR application, or SI5335D-B04375-GMR equivalent, key selection criteria include its dual PLL loop bandwidth options (475 kHz / 1.6 MHz), loss-of-signal alarm, five user-assignable control pins (SSENB, RESET, FS[1:0], OEB), and factory-programmable configuration via ClockBuilder Pro - all critical for PCIe jitter attenuation, DSL synchronization, and FPGA/processor clocking designs.

Technical Context

The SI5335D-B04375-GMR implements a single PLL architecture with four independent MultiSynth fractional dividers per output bank, enabling any-frequency synthesis without integer constraints. Its input supports 10–350 MHz differential (LVDS/LVPECL/CML/HSTL) or 10–200 MHz single-ended (CMOS/SSTL) references, plus 25/27 MHz crystals.

Two selectable PLL loop bandwidths (475 kHz for DSL jitter attenuation; 1.6 MHz for PCIe Gen 3/4) are configured via hardware pins or register settings. Output drivers are independently configurable per bank for voltage (1.5/1.8/2.5/3.3 V), format (LVPECL/LVDS/HCSL/CMOS/SSTL), and enable control - supporting both clock generation and buffer modes with 2.5 ns propagation delay in bypass mode.

Key Specifications

Pinout & Package

SI5335D-B04375-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet, with dedicated input (XA/CLKIN, XB/CLKINB), four output banks (CLK0A/B through CLK3A/B), control pins (P1–P6), LOS alarm, and supply rails (VDD, VDDO0–VDDO3, GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5338A-D-GM and ICS8430I-01T, SI5335D-B04375-GMR uniquely combines web-customizable any-frequency synthesis, 0 ppm error, and PCIe Gen 4 compliance in a compact 24-QFN - making it optimal for dynamic multi-protocol systems requiring field-upgradable timing.

Availability

SI5335D-B04375-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch design, DSLAM synchronization, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle support, and factory-programmed configuration delivery.

Supply support for SI5335D-B04375-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly flexible, web-customizable clock generators targeting high-speed serial interface timing - specifically engineered to replace multiple discrete oscillators and clock ICs in PCIe, Ethernet, DSL, and broadcast video systems.

FAQ

What is the primary function of the SI5335D-B04375-GMR?

The SI5335D-B04375-GMR is a quad-output, web-customizable clock generator/buffer IC that synthesizes four independent, non-integer-related frequencies up to 350 MHz with 0 ppm frequency error. It operates in either clock generator mode (using its internal PLL) or buffer mode (PLL bypass), supporting LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL output formats - making it ideal for replacing multiple oscillators in PCIe, DSL, and FPGA timing applications.

Does the SI5335D-B04375-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04375-GMR is PCIe Gen 4 common clock compliant, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) at 100 MHz HCSL output with 1.6 MHz PLL loop bandwidth. It meets the PCI-SIG Base Specification 4.0 rev. 0.5 jitter limits for Gen 4 common clock architectures and supports spread spectrum control for EMI reduction - validated using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

How many configuration options does the SI5335D-B04375-GMR support?

The SI5335D-B04375-GMR supports three independent, pin-selectable device configurations via FS1 and FS0 control inputs. Each configuration can define unique output frequencies, formats, voltages, and enable states - allowing one physical device to serve as three distinct clock generators in different system modes or operating conditions without firmware update.

What is the role of the LOS pin on the SI5335D-B04375-GMR?

The LOS (Loss-of-Signal) pin on the SI5335D-B04375-GMR is an open-drain, active-low output that asserts within 5 µs of detecting failure on the primary reference input (XA/XB). It provides real-time monitoring of clock integrity and enables system-level fault handling - such as triggering failover to a backup reference or initiating safe shutdown - critical for telecom line cards and industrial control systems requiring high reliability.

Can the SI5335D-B04375-GMR operate with a crystal reference?

Yes, the SI5335D-B04375-GMR supports 25 MHz or 27 MHz fundamental-mode crystals directly connected to the XA/XB pins. The device integrates on-chip load capacitance (18 pF) and crystal drive circuitry, eliminating external components. Crystal specifications require ESR ≤100 Ω (25 MHz) or ≤75 Ω (27 MHz) and max drive level ≤100 µW - ensuring stable startup and low-phase-noise operation.