Skyworks Solutions Inc. SI5335D-B04424-GMR

Overview

SI5335D-B04424-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis. It delivers four independent, non-integer-related output frequencies up to 350 MHz, supports LVPECL/LVDS/HCSL/CMOS/SSTL outputs, achieves 0.7 ps RMS phase jitter, and operates across –40 to +85 °C in PCIe Gen 1–4 and DSL jitter-attenuation systems.

For engineers reviewing the SI5335D-B04424-GMR datasheet, SI5335D-B04424-GMR pinout, SI5335D-B04424-GMR application, or SI5335D-B04424-GMR equivalent, key selection factors include its dual PLL loop bandwidth (475 kHz / 1.6 MHz), loss-of-signal alarm, five user-assignable control pins, and factory-programmable configuration via ClockBuilder Pro - all in a 4 × 4 mm 24-QFN package.

Technical Context

The SI5335D-B04424-GMR integrates a single high-performance PLL with patented MultiSynth fractional dividers per output bank, enabling independent frequency synthesis without integer constraints. Its architecture supports both clock generator mode (full synthesis) and buffer mode (PLL bypass), with input flexibility including 25/27 MHz crystal, CMOS (10–200 MHz), or differential (10–350 MHz) references.

Two selectable PLL loop bandwidths (475 kHz for DSL jitter attenuation; 1.6 MHz for PCIe Gen 3/4) are implemented via hardware pins (P5/P6). Output drivers are independently configurable per bank for voltage (1.5/1.8/2.5/3.3 V), format (LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL), and enable control - supporting up to eight single-ended or four differential clocks simultaneously.

Key Specifications

Pinout & Package

SI5335D-B04424-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet Figure 2 (Top View) and Table 10 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345B-D06489-GM and ICS8430I-01T, the SI5335D-B04424-GMR uniquely balances 4-output flexibility, 0.7 ps RMS jitter, PCIe/DSL compliance, and 4×4 mm footprint - making it optimal for mid-tier networking and FPGA-based embedded systems where BOM consolidation and design agility are prioritized over maximum frequency or absolute lowest jitter.

Availability

SI5335D-B04424-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, DSLAM jitter attenuation, and FPGA processor clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5335D-B04424-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5335 product line was designed as a highly configurable, web-customizable clock generator/buffer family targeting PCIe, Ethernet, DSL, and broadcast video systems - emphasizing BOM reduction, jitter performance, and rapid time-to-market via ClockBuilder Pro.

FAQ

What is the primary function of the SI5335D-B04424-GMR in a PCIe Gen 4 system?

The SI5335D-B04424-GMR serves as a common clock generator delivering up to four low-jitter outputs (e.g., 100 MHz HCSL) compliant with PCIe Gen 4 specifications. It achieves ≤0.45 ps RMS jitter using its 1.6 MHz PLL loop bandwidth and built-in spread spectrum control, eliminating need for external jitter cleaners while supporting direct connection to root complex and endpoint devices.

Does the SI5335D-B04424-GMR support crystal input, and what frequencies are qualified?

Yes, the SI5335D-B04424-GMR supports on-chip crystal oscillator circuitry for 25 MHz and 27 MHz fundamental-mode crystals. The device specifies 18 pF internal load capacitance, ≤100 Ω ESR (25 MHz) or ≤75 Ω ESR (27 MHz), and ≤100 µW drive level - enabling direct crystal connection without external components.

How many independent output voltage supplies does the SI5335D-B04424-GMR support?

The SI5335D-B04424-GMR supports four independent output buffer supply rails (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous interfacing with mixed-voltage devices - for example, 1.8 V FPGA I/O banks and 3.3 V legacy peripherals - without external level shifters.

Can the SI5335D-B04424-GMR operate in clock buffer mode, and what are the key characteristics?

Yes, the SI5335D-B04424-GMR supports PLL bypass (buffer) mode with <4 ns input-to-output propagation delay and 12 mA core current. In this mode, it passes through the input reference with minimal added jitter, supports input frequencies down to 5 MHz, and retains loss-of-signal detection - ideal for low-latency, low-power clock distribution.

What control pin functions are available on the SI5335D-B04424-GMR, and how are they assigned?

The SI5335D-B04424-GMR provides six multi-function pins (P1–P6), with P5 and P6 dedicated to loop bandwidth selection (475 kHz / 1.6 MHz). Remaining pins are user-assignable as SSENB (spread spectrum enable), RESET, FS[1:0] (frequency plan select), or OEB0–OEB3 (individual output enables) - configured via ClockBuilder Pro and locked at factory programming.