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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5335D-B04426-GMR

Name: SI5335D-B04426-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5335D-B04426-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5335D-B04426-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5335D-B04426-GMR.pdf

Description:: IC 4OUT ANY FREQ <200MHZ 24QFN

Quantity:: RFQ Add To RFQ list

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Inventory:4,957

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Product details

Overview

SI5335D-B04426-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis. It delivers four independent, non-integer-related output frequencies up to 350 MHz, supports LVPECL/LVDS/HCSL/CMOS/SSTL outputs, achieves 0.7 ps RMS phase jitter, and operates across –40 to +85 °C in PCIe Gen 1–4 timing systems.

For engineers reviewing the SI5335D-B04426-GMR datasheet, SI5335D-B04426-GMR pinout, SI5335D-B04426-GMR application, or SI5335D-B04426-GMR equivalent, key selection factors include its 24-QFN package, dual PLL loop bandwidth (1.6 MHz / 475 kHz), loss-of-signal alarm, five user-assignable control pins, and PCIe Gen 3 SRNS compliance.

Technical Context

The SI5335D-B04426-GMR integrates a high-performance PLL with two selectable loop bandwidths (1.6 MHz for PCIe jitter attenuation, 475 kHz for DSL applications) and four independent MultiSynth fractional dividers. Each output bank supports differential or single-ended formats with per-driver voltage selection (1.5/1.8/2.5/3.3 V).

It accepts multiple reference inputs: 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz). Pin-selectable configurations (FS[1:0]) enable three distinct frequency plans, while P1–P6 support spread spectrum enable, reset, master/output enables, and frequency plan selection.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	4 banks: each supports 1 differential pair or 2 single-ended outputs - enables flexible clock tree distribution without external fanout buffers
Max Output Frequency	350 MHz (LVPECL/LVDS/CML) - supports 10 GbE, PCIe Gen 4, and broadcast video timing
Phase Jitter (RMS)	0.7 ps (12 kHz–20 MHz) - meets PCIe Gen 3 SRNS and OC-12 jitter requirements
PLL Loop Bandwidth	1.6 MHz or 475 kHz - selectable via pin configuration for optimal jitter filtering in PCIe vs. DSL applications
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.4–3.63 V - allows mixed-voltage system integration with independent output driver biasing
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm - compact footprint compatible with high-density FPGA/ASIC timing layouts

Pinout & Package

The SI5335D-B04426-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin functions are fully configurable via hardware strapping and ClockBuilder Pro customization.

Pin/Terminal	Circuit Role	Design Meaning
XA/CLKIN, XB/CLKINB (Pins 1, 2)	Differential reference input	Accepts 10–350 MHz AC-coupled LVDS/LVPECL/HCSL/CML; internal 10 kΩ termination enables direct connection to crystal oscillator or clock source
CLK0A/CLK0B to CLK3A/CLK3B (Pins 3–4, 6–7, 10–11, 13–14)	Differential clock outputs	Four independent banks; each pair configurable as LVPECL, LVDS, HCSL, or CML with programmable swing and common-mode voltage
VDDO0–VDDO3 (Pins 5, 8, 12, 15)	Output buffer supply rails	Independent 1.4–3.63 V supplies per bank - enables mixed-signaling (e.g., LVDS + HCSL) on same device
P1–P3, P5–P6 (Pins 16–18, 21–22)	Multi-function control inputs	Configurable as SSENB, RESET, OEB_all, OEB0–OEB3, or FS[1:0] - eliminates need for external GPIO logic
LOS (Pin 8)	Loss-of-signal indicator	Open-drain active-low output asserts within 5 µs of CLKIN failure - enables system-level fault detection and failover
VDD (Pins 9, 19)	Core supply	Single 1.8/2.5/3.3 V rail powers PLL and digital logic - high PSRR minimizes supply noise coupling into clock outputs
GND (Pins 17, 20, 23–24)	Ground terminals	Multiple dedicated ground pins plus thermal pad - ensures low-impedance return paths for analog and digital domains

Key Features

Feature	Design Value
0 ppm synthesis error	Guaranteed exact frequency generation across all four outputs using MultiSynth fractional division - eliminates need for multiple crystals or trimming
Three pin-selectable configurations	Hardware-strapped frequency plans (FS[1:0]) allow one device to serve three distinct system states - reduces BOM count and simplifies firmware updates
PCIe Gen 3 SRNS compliance	Validated 0.11–0.32 ps RMS jitter under Separate Reference No Spread conditions - meets strict serial link timing budgets without external jitter cleaners
Programmable output voltage per bank	Independent VDDOx rails (1.5/1.8/2.5/3.3 V) enable simultaneous LVDS (2.5 V) and HCSL (1.8 V) outputs - avoids level-shifter components
Low-power buffer mode	12 mA core current in PLL-bypass mode - ideal for low-jitter clock distribution where synthesis is not required

Applications

PCI Express Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and root complexes in a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator with PCIe Gen 4 common clock compliance and SRNS support. Use Value: Eliminates four discrete oscillators; 0.7 ps RMS jitter ensures <0.45 ps RMS requirement at receiver CDR is met without margin loss.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and switch fabric in a modular Ethernet switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer delivering integer- and non-integer-related rates from single reference. Use Value: Replaces three separate clock ICs; independent MultiSynth banks prevent crosstalk between data path and management interface clocks.
Broadcast Video Synchronization	Telecom Line Card Timing
Use Scenario: Distributing SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks across video encoder, decoder, and transport layers in an IP-based broadcast encoder. IC Role / Device Role / Timing Role: Low-jitter, multi-format clock generator supporting LVDS and HCSL outputs. Use Value: 0.7 ps RMS jitter preserves eye diagram integrity over long PCB traces; HCSL outputs drive backplane loads directly.	Use Scenario: Supplying 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) derived clocks to SerDes and framer ICs in a carrier-grade DSLAM line card. IC Role / Device Role / Timing Role: Jitter-attenuating clock generator with 475 kHz PLL bandwidth for telecom spectral purity. Use Value: Meets ITU-T G.823/G.8262 wander and jitter masks; loss-of-signal alarm triggers automatic switchover to backup timing source.

PCI Express Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and root complexes in a server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator with PCIe Gen 4 common clock compliance and SRNS support.

Use Value: Eliminates four discrete oscillators; 0.7 ps RMS jitter ensures <0.45 ps RMS requirement at receiver CDR is met without margin loss.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and switch fabric in a modular Ethernet switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer delivering integer- and non-integer-related rates from single reference.

Use Value: Replaces three separate clock ICs; independent MultiSynth banks prevent crosstalk between data path and management interface clocks.

Broadcast Video Synchronization

Telecom Line Card Timing

Use Scenario: Distributing SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks across video encoder, decoder, and transport layers in an IP-based broadcast encoder.

IC Role / Device Role / Timing Role: Low-jitter, multi-format clock generator supporting LVDS and HCSL outputs.

Use Value: 0.7 ps RMS jitter preserves eye diagram integrity over long PCB traces; HCSL outputs drive backplane loads directly.

Use Scenario: Supplying 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) derived clocks to SerDes and framer ICs in a carrier-grade DSLAM line card.

IC Role / Device Role / Timing Role: Jitter-attenuating clock generator with 475 kHz PLL bandwidth for telecom spectral purity.

Use Value: Meets ITU-T G.823/G.8262 wander and jitter masks; loss-of-signal alarm triggers automatic switchover to backup timing source.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-D-GM	4-output, lower max frequency (200 MHz), integrated crystal option, no LOS pin	Better suited for cost-sensitive, lower-frequency applications without loss-of-signal monitoring	Select when system requires crystal integration and does not need >200 MHz outputs or LOS alarm
ICS853S01AGI-01LFT	Quad LVDS output only, fixed 100/125/156.25 MHz outputs, no frequency synthesis	Limited to standard Ethernet/PCIe frequencies; no custom frequency support	Select only for fixed-frequency, low-complexity clock fanout where synthesis flexibility is unnecessary

Compared with Si5338A-D-GM and ICS853S01AGI-01LFT, the SI5335D-B04426-GMR uniquely combines any-frequency synthesis up to 350 MHz, loss-of-signal detection, and per-bank voltage control - making it the only option for PCIe Gen 4 timing with dynamic reconfiguration and robust fault monitoring.

Availability

SI5335D-B04426-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10/25 GbE switch designs, and telecom line cards requiring stable component supply, factory-programmed configurations, and long-term lifecycle support.

Supply support for SI5335D-B04426-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5335 product line was designed specifically for high-flexibility, low-jitter clock generation in multi-protocol systems such as PCIe, Ethernet, and telecom equipment - emphasizing web-customizability, pin-controlled configuration, and jitter performance across diverse signaling standards.

FAQ

What is the maximum output frequency supported by the SI5335D-B04426-GMR?

The SI5335D-B04426-GMR supports up to 350 MHz on LVPECL, LVDS, and CML outputs, and up to 250 MHz on HCSL outputs. These limits are defined by the output driver architecture and have been validated across temperature and voltage ranges per Skyworks' electrical specifications. The SI5335D-B04426-GMR achieves this while maintaining 0.7 ps RMS phase jitter in generator mode.

Does the SI5335D-B04426-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04426-GMR is compliant with PCIe Gen 4 common clock specifications, delivering ≤0.45 ps RMS jitter (10 kHz–50 MHz) under specified test conditions. Its 1.6 MHz PLL bandwidth and MultiSynth synthesis engine meet the stringent random jitter and period jitter requirements outlined in the PCI-SIG Base Specification 4.0 rev. 0.5.

How many independent frequency plans can be configured on the SI5335D-B04426-GMR?

The SI5335D-B04426-GMR supports three independent, pin-selectable device configurations via FS[1:0] control pins. Each configuration defines unique output frequencies, formats, and voltage settings - enabling dynamic switching between system modes (e.g., normal operation, low-power standby, and test mode) without firmware intervention.

What reference inputs are compatible with the SI5335D-B04426-GMR?

The SI5335D-B04426-GMR accepts 25 or 27 MHz crystals directly, or AC-coupled CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) clock inputs. Input impedance is 10 kΩ with 3.5 pF capacitance, and loss-of-signal detection activates within 5 µs for all supported references.

Is the SI5335D-B04426-GMR available in a lead-free, RoHS-compliant package?

Yes, the SI5335D-B04426-GMR is manufactured in a RoHS-compliant, lead-free 24-QFN package (4 × 4 mm) with NiPdAu terminal finish. Skyworks confirms full compliance with EU RoHS Directive 2011/65/EU and JEDEC JS-001 ESD standards, and the device carries the "GMR" suffix denoting green, halogen-free construction.

SI5335D-B04426-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5335D-B04426-GMR FAQ

1.How can I place an order for SI5335D-B04426-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5335D-B04426-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5335D-B04426-GMR reliable?

The price and inventory of SI5335D-B04426-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5335D-B04426-GMR is usually 5 days.

3.What payment methods are accepted for SI5335D-B04426-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5335D-B04426-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5335D-B04426-GMR?

SI5335D-B04426-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5335D-B04426-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5335D-B04426-GMR?

For technical support, including SI5335D-B04426-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5335D-B04426-GMR requirements.

6.How does Aetrix verify that SI5335D-B04426-GMR is sourced from the original manufacturer or authorized distributors?

All SI5335D-B04426-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5335D-B04426-GMR meets industry standards.

7.What is the process for return or replacement of SI5335D-B04426-GMR?

All SI5335D-B04426-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5335D-B04426-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5335D-B04426-GMR part is unused and in its original packaging.

Return procedure for SI5335D-B04426-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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