Skyworks Solutions Inc. SI5335D-B04487-GMR

Overview

SI5335D-B04487-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL/CML output formats. It serves as a single-chip timing solution in high-speed serial interface clocking systems.

For engineers reviewing the SI5335D-B04487-GMR datasheet, SI5335D-B04487-GMR pinout, SI5335D-B04487-GMR application, or SI5335D-B04487-GMR equivalent, this device delivers precise multi-frequency synthesis with programmable loop bandwidth (1.6 MHz / 475 kHz), loss-of-signal detection, spread spectrum control, and flexible input reference options including 25/27 MHz crystal, CMOS, SSTL, HSTL, or differential inputs.

Technical Context

The SI5335D-B04487-GMR integrates four independent MultiSynth fractional-N synthesizers, each driving one differential pair or two single-ended outputs, with guaranteed 0 ppm frequency synthesis error across all configurations. Its dual-loop-bandwidth PLL supports jitter attenuation for PCIe and DSL applications.

It features five user-assignable control pins (P1–P3, P5, P6) supporting spread spectrum enable (SSENB), master/output enables (OEB), frequency plan selection (FS1/FS0), and reset. The device operates in either clock generator mode (45 mA core current) or low-power buffer mode (12 mA core current), with independent VDDO per output bank (1.5/1.8/2.5/3.3 V).

Key Specifications

Pinout & Package

SI5335D-B04487-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow the standard Si5335 top-view layout and are validated per Skyworks Rev. 1.4 datasheet (pages 2, 10, 38–40).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5341-A01AGM and ICS8430I-01LG, the SI5335D-B04487-GMR uniquely balances field-programmable frequency agility, PCIe Gen 4 compliance, and pin-controlled configuration - making it optimal for rapidly evolving compute and networking platforms requiring both flexibility and certification-ready jitter performance.

Availability

SI5335D-B04487-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10/25/100 GbE switch designs, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5335D-B04487-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clock innovation.

The SI5335 family was designed specifically for high-speed serial interface timing in datacenter, telecom, and broadcast applications - delivering web-customizable, any-frequency clock generation with best-in-class jitter and multi-protocol output flexibility.

FAQ

What is the primary function of the SI5335D-B04487-GMR?

The SI5335D-B04487-GMR is a quad-output, web-customizable clock generator/buffer IC that synthesizes up to four independent, non-integer-related frequencies (1–350 MHz) with 0.7 ps RMS phase jitter. It replaces multiple oscillators and clock ICs in systems requiring precise, flexible timing - such as PCIe Gen 4, Ethernet switches, and broadcast video equipment. Its MultiSynth technology guarantees zero ppm frequency error across all configurations.

Does the SI5335D-B04487-GMR support PCIe Gen 4 common clock compliance?

Yes, the SI5335D-B04487-GMR meets PCIe Gen 4 common clock jitter requirements with ≤0.45 ps RMS (12 kHz–20 MHz) when configured with 1.6 MHz loop bandwidth and HCSL outputs. It is explicitly listed as PCIe Gen 1/2/3/4 common clock compliant and SRNS-compliant for Gen 3 in the official Skyworks datasheet Rev. 1.4, validated using Intel Clock Jitter Tool v1.6.4.

How many output formats does the SI5335D-B04487-GMR support per bank?

The SI5335D-B04487-GMR supports LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL output formats - selectable per bank. Each of its four output banks can be configured for one differential pair (e.g., CLK0A/CLK0B) or two single-ended outputs (e.g., CLK0A and CLK0B as separate CMOS signals), enabling mixed-format clock distribution on a single device.

What input reference options are available for the SI5335D-B04487-GMR?

The SI5335D-B04487-GMR accepts multiple input references: 25 MHz or 27 MHz fundamental-mode crystals (internal 18 pF load), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential inputs (LVDS/LVPECL/HCSL/CML, 10–350 MHz). All inputs support loss-of-signal detection with 2.6–5 µs response time, critical for redundant clock architectures.

Can the SI5335D-B04487-GMR operate in low-power buffer mode?

Yes, the SI5335D-B04487-GMR supports a dedicated buffer mode (PLL bypass) with only 12 mA core supply current - less than 27% of its 45 mA clock generator mode consumption. In this mode, it provides jitter-cleaned, frequency-translated outputs with propagation delay of 2.5–4 ns, ideal for clock distribution without synthesis overhead in power-constrained systems.