Skyworks Solutions Inc. SI5335D-B04548-GMR

Overview

SI5335D-B04548-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, 0 ppm synthesis error via MultiSynth fractional divider technology, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and operation across –40 to +85 °C. It serves as a single-device replacement for multiple crystal oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335D-B04548-GMR datasheet, SI5335D-B04548-GMR pinout, SI5335D-B04548-GMR application, or SI5335D-B04548-GMR equivalent, key selection considerations include its four configurable differential/single-ended output banks, dual PLL loop bandwidth options (475 kHz / 1.6 MHz), loss-of-signal alarm, five user-assignable control pins, and factory-programmed configuration via ClockBuilder Pro.

Technical Context

The SI5335D-B04548-GMR implements a single PLL core with four independent MultiSynth fractional-N dividers per output bank, enabling simultaneous synthesis of unrelated frequencies without integer constraints. Its architecture supports both clock generator mode (PLL active) and low-jitter clock buffer mode (PLL bypass), with input flexibility including 25/27 MHz crystals or AC-coupled differential/single-ended references from 10–350 MHz.

Control logic integrates five multi-function pins (P1–P3, P5–P6) supporting spread spectrum enable (SSENB), master/output enables (OEB), frequency plan selection (FS1/FS0), and reset. The device features programmable output voltage per bank (1.5/1.8/2.5/3.3 V), configurable driver formats (LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL), and loss-of-signal detection with 2.6–5 µs response time.

Key Specifications

Pinout & Package

SI5335D-B04548-GMR uses a 24-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet, with dedicated input (XA/CLKIN, XB/CLKINB), output (CLK0A–CLK3B), supply (VDD, VDDO0–VDDO3), control (P1–P3, P5–P6), and status (LOS) terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345A-D-GM and ICS853S01AGI-01LFT, the SI5335D-B04548-GMR uniquely balances four fully independent synthesized outputs, PCIe Gen 4 compliance, and compact 24-QFN packaging-making it optimal for mid-tier switch/router and FPGA-based embedded timing where BOM simplification and pin-count efficiency are critical.

Availability

SI5335D-B04548-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, 10G/25G Ethernet switches, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and factory-programmed configuration.

Supply support for SI5335D-B04548-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5335 family is designed for high-performance, multi-protocol timing in datacenter, telecom, and broadcast equipment-enabling consolidation of discrete clock sources into a single programmable IC with zero-frequency-error synthesis.

FAQ

What is the primary function of the SI5335D-B04548-GMR in a PCIe Gen 4 system?

The SI5335D-B04548-GMR serves as a common clock generator compliant with PCIe Gen 4 specifications, delivering up to four low-jitter (≤0.45 ps RMS) output clocks-including 100 MHz HCSL-while supporting SRNS mode with a 2–5 MHz CDR bandwidth. Its 1.6 MHz PLL loop bandwidth and MultiSynth architecture ensure precise frequency synthesis without integer constraints, directly meeting the Base Specification 4.0 rev. 0.5 jitter requirements for root complex timing.

Does the SI5335D-B04548-GMR support spread spectrum clocking (SSC)?

Yes, the SI5335D-B04548-GMR supports spread spectrum clocking via the SSENB control pin. It provides –0.45% to –0.5% down-spread modulation at a default rate of 31.5 kHz-optimized for PCI compliance. SSC can be enabled or disabled dynamically during operation, and the modulation depth and rate are factory-configurable through ClockBuilder Pro prior to shipment.

How many independent output voltage supplies does the SI5335D-B04548-GMR support?

The SI5335D-B04548-GMR supports four independent output buffer supply rails (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows mixed-signal boards to drive LVPECL (3.3 V), LVDS (2.5 V), HCSL (1.8 V), and CMOS (1.5 V) loads simultaneously without external level shifters, reducing design complexity and board area.

Can the SI5335D-B04548-GMR operate as a pure clock buffer without PLL synthesis?

Yes, the SI5335D-B04548-GMR supports PLL bypass mode, functioning as a low-jitter (≤0.7 ps RMS), four-bank clock buffer with 12 mA core current draw. In this mode, input clocks pass through with minimal added jitter (2.5–4 ns propagation delay), and loss-of-signal detection remains active. This mode is ideal for applications requiring clean distribution of an existing reference without frequency translation.

What is the role of the LOS pin on the SI5335D-B04548-GMR?

LOS (Pin 20) is an open-drain loss-of-signal indicator that asserts low within 2.6–5 µs of CLKIN failure. It monitors the differential input (XA/XB) and signals upstream system controllers of reference clock loss, enabling fail-safe responses such as switching to backup timing or initiating reset sequences. An external pull-up resistor is required for proper logic-level operation.