Skyworks Solutions Inc. SI5335D-B04565-GMR

Overview

SI5335D-B04565-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC with MultiSynth fractional synthesis. It delivers four independent, non-integer-related output frequencies up to 350 MHz, supports LVPECL/LVDS/HCSL/CMOS/SSTL outputs, achieves 0.7 ps RMS phase jitter, and operates across –40 to +85 °C in a 4 × 4 mm 24-QFN package - deployed in PCIe Gen 4 timing, Ethernet switch clocking, and FPGA synchronization.

For engineers reviewing the SI5335D-B04565-GMR datasheet, SI5335D-B04565-GMR pinout, SI5335D-B04565-GMR application, or SI5335D-B04565-GMR equivalent, key selection considerations include its dual PLL loop bandwidth (475 kHz / 1.6 MHz), loss-of-signal alarm, five user-assignable control pins (FS0/FS1, SSENB, RESET, OEB), and PCIe Gen 3 SRNS / Gen 4 common-clock compliance.

Technical Context

The SI5335D-B04565-GMR implements a single high-performance PLL with patented MultiSynth fractional dividers per output bank, enabling independent frequency synthesis without integer constraints. Its architecture supports both clock generator mode (full synthesis) and buffer mode (PLL bypass), with input flexibility including 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references.

Output stage configuration is per-bank: each of four banks provides either one differential pair or two single-ended clocks, with independent VDDO voltage selection (1.5/1.8/2.5/3.3 V) and format assignment (LVPECL, LVDS, CML, HCSL, CMOS, SSTL, HSTL). Control logic includes pin-selectable frequency plans, spread-spectrum enable, master/output-specific enables, and loss-of-signal detection with sub-5 µs response.

Key Specifications

Pinout & Package

SI5335D-B04565-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet (pp. 38–40).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345A-D06181-GM and ICS8430I-01T, SI5335D-B04565-GMR uniquely balances web-customizable any-frequency synthesis, PCIe Gen 4 readiness, and hardware pin control - making it optimal for mid-tier servers, enterprise switches, and FPGA-based embedded systems needing flexibility without over-specification.

Availability

SI5335D-B04565-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, Ethernet switch clocking, and FPGA synchronization requiring stable component supply, long-term lifecycle assurance, and factory-programmed configuration traceability.

Supply support for SI5335D-B04565-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly flexible, web-customizable clock generators targeting multi-protocol systems requiring PCIe, Ethernet, and processor timing - designed to replace multiple discrete oscillators and clock ICs with a single programmable device.

FAQ

What is the primary function of the SI5335D-B04565-GMR in a timing architecture?

The SI5335D-B04565-GMR serves as a quad-output clock generator/buffer that synthesizes four independent, non-integer-related frequencies up to 350 MHz using Skyworks' MultiSynth fractional divider technology. It replaces multiple discrete oscillators and clock ICs in systems such as PCIe Gen 4 servers and Ethernet switches, delivering 0.7 ps RMS phase jitter and hardware-configurable frequency plans - all within a single 4 × 4 mm QFN package.

Does the SI5335D-B04565-GMR support PCIe Gen 4 common-clock compliance?

Yes, the SI5335D-B04565-GMR is validated for PCIe Gen 4 common-clock compliance with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) under specified test conditions (100 MHz HCSL outputs, 1.6 MHz PLL loop bandwidth). It meets the TIJ specification for root complex and endpoint timing in Gen 4 systems and supports spread-spectrum clocking per PCIe Base Spec 4.0.

How many user-assignable control pins does the SI5335D-B04565-GMR have, and what functions can they perform?

The SI5335D-B04565-GMR provides five user-assignable control pins (P1, P2, P3, P5, P6) that support functions including frequency plan selection (FS0/FS1), spread-spectrum enable (SSENB), master or individual output enable (OEB), and device reset. These pins allow hardware-based configuration switching without I²C communication - enabling field-upgradable timing modes and simplified system-level control.

What output formats and voltage levels are supported by the SI5335D-B04565-GMR?

The SI5335D-B04565-GMR supports LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL output formats across four independent banks. Each bank has its own VDDO supply (1.5/1.8/2.5/3.3 V), allowing mixed-voltage operation - for example, 1.8 V LVDS for SerDes and 3.3 V CMOS for legacy peripherals - without external level shifters.

Is the SI5335D-B04565-GMR pin-compatible with other devices in the Si5335 family?

Yes, all Si5335 variants - including SI5335D-B04565-GMR - share identical 24-QFN packaging, pinout, and footprint per Skyworks' package outline (Rev. 1.4, p. 42). This enables hardware reuse across different frequency/configurations, provided the firmware and ClockBuilder Pro configuration match the target application's timing requirements.