Skyworks Solutions Inc. SI5335D-B04718-GMR
- Part No.:
- SI5335D-B04718-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5335D-B04718-GMR.pdf
- Description:
- IC 4OUT ANY FREQ <200MHZ 24QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5335D-B04718-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, low phase jitter of 0.7 ps RMS, PCIe Gen 1–4 common clock compliance, and configurable output formats (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL/CML) per bank. It serves as a single-device replacement for multiple clock ICs in high-speed serial interface timing systems.
For engineers reviewing the SI5335D-B04718-GMR datasheet, SI5335D-B04718-GMR pinout, SI5335D-B04718-GMR application, or SI5335D-B04718-GMR equivalent, key selection criteria include its MultiSynth fractional synthesis architecture, dual PLL loop bandwidth options (1.6 MHz / 475 kHz), loss-of-signal alarm, five user-assignable control pins, and factory-programmable configuration via ClockBuilder Pro.
Technical Context
The SI5335D-B04718-GMR implements Skyworks' patented MultiSynth fractional divider technology across four independent synthesis paths, guaranteeing 0 ppm frequency synthesis error regardless of output frequency or format combination. Its dual-loop-bandwidth PLL supports jitter attenuation for PCIe (1.6 MHz) and DSL (475 kHz) applications.
Input flexibility includes external crystal (25/27 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references. Each of the four output banks supports one differential pair or two single-ended outputs, with independent voltage selection (1.5/1.8/2.5/3.3 V) and format assignment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count & Type | Four banks: each supports 1 differential pair or 2 single-ended outputs; total up to 4 differential or 8 single-ended clocks |
| Max Output Frequency | 350 MHz for LVPECL/LVDS/CML/SSTL/HSTL; 250 MHz for HCSL; 200 MHz for CMOS |
| Phase Jitter (RMS) | 0.7 ps RMS (12 kHz–20 MHz), measured with LVDS/HCSL/LVPECL/CML outputs and low-noise differential input |
| PLL Loop Bandwidth | Selectable 1.6 MHz (PCIe jitter attenuation) or 475 kHz (DSL jitter attenuation) |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per bank |
| Operating Temp | –40 °C to +85 °C, qualified for industrial embedded and telecom line card environments |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
The SI5335D-B04718-GMR is housed in a 24-lead QFN package (4 mm × 4 mm) with an exposed thermal pad. Pin assignments are fixed per the Si5335 family specification and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 (XA/CLKIN, XB/CLKINB) | Differential reference input | Accepts AC-coupled LVDS/LVPECL/HCSL/CML (10–350 MHz); internal 10 kΩ termination; supports crystal oscillator mode with 25/27 MHz crystals |
| 3–4, 6–7, 10–11, 13–14 (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B) | Differential clock outputs | Four independent banks; each pair configurable as LVPECL/LVDS/HCSL/CML with per-bank VDDO voltage and format selection |
| 5, 8, 9, 12, 15–16, 18–24 (VDD, VDDO0–3, GND, LOS, P1–P6, RSVD_GND) | Power, control, and status | VDD core supply (1.8/2.5/3.3 V); VDDOx per-output-bank supplies (1.5–3.3 V); LOS open-drain alarm; five multi-function pins (P1–P3, P5–P6) for OEB, SSENB, FS[1:0], RESET |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Four independent outputs with 0 ppm frequency error using MultiSynth fractional dividers, enabling replacement of multiple discrete clock sources |
| Configurable device modes | Supports clock generator (PLL active), clock buffer (PLL bypass), or hybrid operation - selectable via pin or register |
| Flexible output stage | Per-bank voltage (1.5/1.8/2.5/3.3 V) and format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL/CML) assignment eliminates level-shifting components |
| PCIe Gen 4 compliance | Meets PCIe Gen 4 common clock jitter requirements (≤0.45 ps RMS) with 1.6 MHz loop bandwidth and HCSL 100 MHz outputs |
| User-assignable control pins | Five pins (P1–P3, P5–P6) support spread spectrum enable, master/output-specific OEB, frequency plan select (FS1/FS0), and reset - simplifying system-level control logic |
Applications
| PCI Express Gen 1–4 Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized reference clocks to multiple PCIe endpoints (e.g., GPU, NVMe, switch fabric) in a server motherboard with strict jitter budgets. IC Role / Device Role / Timing Role: Quad-output common clock generator with PCIe Gen 4-compliant jitter performance and spread spectrum support. Use Value: Eliminates need for four separate oscillators or buffers; reduces BOM count and layout complexity while meeting PCIe SRNS and common clock specs. | Use Scenario: Delivering precise, low-jitter clocks to Ethernet PHYs, MACs, and packet processors in 1/10 GbE switches and routers. IC Role / Device Role / Timing Role: Configurable clock source supporting 125 MHz (GbE), 156.25 MHz (10GbE), and 312.5 MHz (25GbE) with LVDS/HCSL outputs. Use Value: Single device generates all required frequencies with <0.7 ps RMS jitter, avoiding inter-clock skew and simplifying power domain isolation. |
| Broadcast Video/Audio Timing | Processor & FPGA Clocking |
Use Scenario: Synchronizing SDI video encoders, audio sample rate converters, and genlock circuits in broadcast equipment requiring SMPTE 2081/2082 compliance. IC Role / Device Role / Timing Role: Multi-format clock generator delivering 27 MHz (SDI), 74.25 MHz (HD-SDI), and 148.5 MHz (3G-SDI) with sub-ps jitter and low duty cycle distortion. Use Value: Replaces crystal oscillators and fanout buffers; supports simultaneous LVPECL (for SerDes) and CMOS (for logic) outputs from same device. | Use Scenario: Supplying core, I/O, and peripheral clocks to heterogeneous SoCs, FPGAs, and ASICs in industrial control or test equipment. IC Role / Device Role / Timing Role: Programmable universal clock buffer/generator with independent voltage and format per output bank for mixed-voltage domains. Use Value: Enables single-chip clock tree for 1.0 V core, 1.8 V I/O, and 3.3 V peripherals - reducing PCB layers and decoupling network size. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05889-GM | Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency | Targeted at JESD204B ADC/DAC timing and ultra-low-jitter 5G infrastructure; requires ClockBuilder Desktop | Choose for JESD204B or sub-0.4 ps jitter needs; not drop-in due to different pinout and EEPROM dependency |
| ICS8430I-01T | Fixed-frequency quad LVDS buffer (no synthesis), 0.8 ps RMS jitter, 3.3 V only, no spread spectrum or LOS alarm | Limited to buffered replication of a single input; no frequency translation or multi-voltage support | Choose only when all outputs require identical frequency and format; lacks SI5335D-B04718-GMR's configurability and flexibility |
Compared with Si5332A-D05889-GM, SI5335D-B04718-GMR offers faster time-to-customization (2-week factory programming) and broader input reference support, while ICS8430I-01T provides simpler, lower-cost buffering where synthesis is unnecessary.
Availability
SI5335D-B04718-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, Ethernet switching, and broadcast video applications requiring stable component supply, long-term lifecycle assurance, and factory-programmed configurations.
Supply support for SI5335D-B04718-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5335 product line delivers highly flexible, web-customizable clock generation for high-speed serial interfaces, designed to replace multiple discrete timing components with a single programmable IC in datacenter, telecom, and broadcast systems.
FAQ
What is the primary function of the SI5335D-B04718-GMR?
The SI5335D-B04718-GMR is a quad-output, any-frequency clock generator/buffer IC that synthesizes four independent, non-integer-related clock frequencies up to 350 MHz using Skyworks' MultiSynth fractional divider technology. It operates as either a full PLL-based generator or a low-latency buffer (PLL bypass mode), and SI5335D-B04718-GMR supports PCIe Gen 1–4, Ethernet, and broadcast timing standards with 0.7 ps RMS phase jitter.
Does the SI5335D-B04718-GMR support spread spectrum clocking?
Yes, the SI5335D-B04718-GMR supports PCIe-compliant spread spectrum clocking via the SSENB control pin. It delivers –0.45% to –0.5% down-spread modulation at 31.5 kHz by default, and this feature is fully configurable through ClockBuilder Pro. The SI5335D-B04718-GMR implements spread spectrum without degrading jitter performance beyond PCIe specifications.
What output formats and voltage levels does the SI5335D-B04718-GMR support?
The SI5335D-B04718-GMR supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, and HSTL output formats across its four banks. Each bank has an independent VDDO supply (1.5 V, 1.8 V, 2.5 V, or 3.3 V), allowing mixed-voltage operation on a single device. For example, CLK0A/B can be LVPECL at 3.3 V while CLK2A/B runs as CMOS at 1.8 V - all simultaneously enabled in SI5335D-B04718-GMR.
How is the SI5335D-B04718-GMR configured for custom frequencies?
The SI5335D-B04718-GMR is factory-configured using Skyworks' ClockBuilder Pro web utility, which generates a custom configuration file based on user-defined input reference, output frequencies, formats, and control pin functions. Once programmed, SI5335D-B04718-GMR operates autonomously with no external programming required - delivering the specified timing solution in as little as two weeks with no MOQ.
What is the role of the LOS (Loss of Signal) pin on the SI5335D-B04718-GMR?
The LOS pin on the SI5335D-B04718-GMR is an open-drain output that asserts low within 2.6–5 µs of detecting loss of valid input clock on XA/XB pins. It provides real-time fault indication for system monitoring and fail-safe clock switchover logic. This feature is active in both PLL and buffer modes and is fully integrated into SI5335D-B04718-GMR's internal detection circuitry without external components.
SI5335D-B04718-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5335D-B04718-GMR FAQ
1.How can I place an order for SI5335D-B04718-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5335D-B04718-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5335D-B04718-GMR reliable?
The price and inventory of SI5335D-B04718-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5335D-B04718-GMR is usually 5 days.
3.What payment methods are accepted for SI5335D-B04718-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5335D-B04718-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5335D-B04718-GMR?
SI5335D-B04718-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5335D-B04718-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5335D-B04718-GMR?
For technical support, including SI5335D-B04718-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5335D-B04718-GMR requirements.
6.How does Aetrix verify that SI5335D-B04718-GMR is sourced from the original manufacturer or authorized distributors?
All SI5335D-B04718-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5335D-B04718-GMR meets industry standards.
7.What is the process for return or replacement of SI5335D-B04718-GMR?
All SI5335D-B04718-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5335D-B04718-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5335D-B04718-GMR part is unused and in its original packaging.
Return procedure for SI5335D-B04718-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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