Skyworks Solutions Inc. SI5335D-B04729-GMR

Overview

SI5335D-B04729-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC supporting four independent non-integer-related frequencies up to 350 MHz, with LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL output formats, 0.7 ps RMS phase jitter, and PCIe Gen 1–4 common-clock compliance - deployed in high-speed serial interface timing for Ethernet switches and FPGA-based compute platforms.

For engineers reviewing the SI5335D-B04729-GMR datasheet, SI5335D-B04729-GMR pinout, SI5335D-B04729-GMR application, or SI5335D-B04729-GMR equivalent, key selection criteria include differential output jitter performance (0.7 ps RMS), configurable loop bandwidth (475 kHz / 1.6 MHz), MultiSynth fractional synthesis accuracy (0 ppm error), and support for three pin-selectable frequency plans in a 24-QFN package.

Technical Context

The SI5335D-B04729-GMR implements four independent MultiSynth fractional-N dividers fed by a single PLL, enabling simultaneous synthesis of unrelated output frequencies without external crystals. Its architecture supports both clock generator mode (PLL active) and low-jitter buffer mode (PLL bypass), with input flexibility across crystal (25/27 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), and differential (10–350 MHz) references.

Two selectable PLL loop bandwidths (475 kHz for DSL jitter attenuation; 1.6 MHz for PCIe Gen 3/4) are controlled via pins P5/P6, while five multi-function control pins (P1–P3, P5, P6) enable spread-spectrum control (SSENB), master/output enables (OEB), frequency plan selection (FS[1:0]), and reset - all configurable via ClockBuilder Pro web utility prior to factory programming.

Key Specifications

Pinout & Package

SI5335D-B04729-GMR is housed in a 24-lead QFN package (4 mm × 4 mm) with exposed thermal pad. Pin functions are fully programmable during configuration; default assignments align with standard Si5335 pinout per Rev. 1.4 datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345A-D-GM and ICS8430I-01T, SI5335D-B04729-GMR uniquely balances web-customizability, 0 ppm synthesis accuracy, and PCIe Gen 4 compliance in a 24-QFN package - making it the most adaptable solution for mid-tier networking and compute platforms requiring field-upgradable timing.

Availability

SI5335D-B04729-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch design, 10 GbE router development, and FPGA-based edge AI inference systems requiring stable component supply, consistent parametric performance, and long-term lifecycle support.

Supply support for SI5335D-B04729-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 family was designed as a highly flexible, web-customizable clock generator platform targeting high-speed serial interface timing - specifically addressing PCIe, Ethernet, and FPGA clocking needs with zero-error synthesis and multi-standard compliance.

FAQ

What is the primary function of the SI5335D-B04729-GMR in a system?

The SI5335D-B04729-GMR serves as a quad-output clock generator/buffer that synthesizes up to four independent, non-integer-related frequencies (1–350 MHz) with 0 ppm error using Skyworks' MultiSynth technology. It replaces multiple discrete oscillators and clock ICs in systems like PCIe switches and Ethernet routers, reducing board space and improving timing margin predictability. Its role is confirmed in the datasheet's "Description" and "Features" sections.

Does the SI5335D-B04729-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04729-GMR is PCIe Gen 4 common-clock compliant, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) with 1.6 MHz loop bandwidth and HCSL outputs - verified in Table 8 of the datasheet under "PCIe Gen 4, Common Clock" test condition. It also supports spread-spectrum modulation and meets TJ < 35 ps pk-pk for Gen 4 applications.

How many output configurations can be stored and selected on the SI5335D-B04729-GMR?

The SI5335D-B04729-GMR supports three independent, pin-selectable device configurations (frequency plans), enabled via FS[1:0] control pins (P5/P6). This allows one physical device to serve three distinct timing roles - e.g., boot mode, normal operation, and test mode - without firmware reprogramming, as documented in Section 3.8 of the datasheet.

What input reference sources does the SI5335D-B04729-GMR accept?

The SI5335D-B04729-GMR accepts four input types: (1) 25 or 27 MHz crystal (internally loaded), (2) CMOS clock (10–200 MHz), (3) SSTL/HSTL clock (10–350 MHz), and (4) differential clock (LVDS/LVPECL/HCSL/CML, 10–350 MHz). Input flexibility is detailed in Section 3.4 and Table 4 of the datasheet, with dedicated pins XA/CLKIN and XB/CLKINB for differential inputs.

Is the SI5335D-B04729-GMR pin-compatible with other Si5335 variants?

Yes, all Si5335 variants - including SI5335D-B04729-GMR - share identical 24-QFN pinout and package dimensions per Section 12 of the datasheet. Pin functions (e.g., CLK0A/B through CLK3A/B, P1–P6, LOS) are consistent across the family; differences lie solely in factory-programmed configuration data, not hardware layout or electrical interface.