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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5335D-B04730-GMR

Name: SI5335D-B04730-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5335D-B04730-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5335D-B04730-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5335D-B04730-GMR.pdf

Description:: IC 4OUT ANY FREQ <200MHZ 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5335D-B04730-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and configurable LVPECL/LVDS/HCSL/CMOS/SSTL outputs. It serves as a single-chip timing solution for multi-clock-domain systems such as PCIe switch fabrics and FPGA-based telecom line cards.

For engineers reviewing the SI5335D-B04730-GMR datasheet, SI5335D-B04730-GMR pinout, SI5335D-B04730-GMR application, or SI5335D-B04730-GMR equivalent, key selection considerations include its MultiSynth fractional synthesis architecture, dual PLL loop bandwidth options (475 kHz / 1.6 MHz), loss-of-signal alarm, five user-assignable control pins, and factory-programmable configuration via ClockBuilder Pro.

Technical Context

The SI5335D-B04730-GMR implements Skyworks' patented MultiSynth fractional divider technology across four independent synthesis paths, enabling zero-ppm frequency error for any output combination within 1–350 MHz. Its dual-loop PLL supports jitter attenuation in both high-bandwidth (PCIe) and low-bandwidth (DSL) applications.

Input flexibility includes 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references. Output drivers support per-bank voltage selection (1.5/1.8/2.5/3.3 V) and format-independent enable control, with loss-of-signal detection on the reference input.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 banks: each supports 1 differential pair or 2 single-ended outputs; up to 4 differential + 8 single-ended total
Max output frequency	350 MHz (LVPECL/LVDS/CML); 250 MHz (HCSL); 200 MHz (CMOS)
Phase jitter (RMS)	0.7 ps (12 kHz–20 MHz, 1.6 MHz loop BW, differential outputs)
PLL loop bandwidth	Selectable 475 kHz or 1.6 MHz - enables optimized jitter filtering for DSL or PCIe applications
Supply voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5–3.3 V per bank
Operating temperature	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments
Package	24-pin QFN, 4 mm × 4 mm - compact footprint compatible with high-density PCB layouts

Pinout & Package

SI5335D-B04730-GMR uses a 24-lead QFN package (4 mm × 4 mm) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet, including dual differential inputs (XA/CLKIN, XB/CLKINB), four differential output pairs (CLK0A/B through CLK3A/B), three dedicated control pins (P1, P2, P3), two dual-function pins (P5, P6), loss-of-signal indicator (LOS), and multiple VDD/VDDO/GND terminals.

Pin/Terminal	Circuit Role	Design Meaning
1, 2 (XA/CLKIN, XB/CLKINB)	Differential reference input	Accepts 10–350 MHz AC-coupled LVDS/LVPECL/HCSL/CML; internal 100 Ω termination enabled
3, 4 (CLK2B, CLK2A)	Differential output bank 2	Configurable format (LVPECL/LVDS/HCSL/CML) and voltage (1.5–3.3 V); individually enableable
5, 6 (CLK1B, CLK1A)	Differential output bank 1	Same configurability as bank 2; supports integer/fractional synthesis with 0 ppm error
7–10 (VDDO2, VDDO1, VDD, VDD)	Power supply rails	VDD = core supply (1.8/2.5/3.3 V); VDDOx = independent output buffer supplies per bank
11, 12 (CLK3A, CLK3B)	Differential output bank 3	Supports HCSL up to 250 MHz or LVDS/LVPECL up to 350 MHz; programmable slew rate
13 (LOS)	Loss-of-signal indicator	Open-drain output asserting low when reference clock fails; 2.6–5 µs detection latency
14–16 (VDDO0, CLK0B, CLK0A)	Output bank 0 + supply	CLK0A/B = first differential output pair; VDDO0 sets its driver voltage independently
17–24 (RSVD_GND, VDDO3, GND, GND, Pad, P1, P2, P3)	Control & ground	P1/P2/P3 = user-assignable pins (OEB, FS[1:0], RESET, SSENB); RSVD_GND = reserved ground

Key Features

Feature	Design Value
MultiSynth fractional synthesis	Enables any-frequency output generation (1–350 MHz) with zero ppm frequency error - eliminates need for multiple crystals or clock ICs
Three pin-selectable configurations	Allows one device to replace up to three discrete clock generators via hardware-selectable frequency plans (FS1/FS0)
Five user-assignable control pins	P1–P3 and P5–P6 support spread-spectrum enable, master/output-specific OEB, reset, and frequency plan selection - reduces external logic
PCIe Gen 1–4 common clock compliance	Meets jitter requirements (e.g., ≤0.45 ps RMS for PCIe Gen 3/4) without external filtering - simplifies PCIe timing validation
Independent output voltage per bank	VDDO0–VDDO3 allow mixed-voltage system interfacing (e.g., 1.8 V FPGA core + 3.3 V legacy PHY) without level shifters

Applications

PCI Express Switch Fabric	Telecom Line Card Timing
Use Scenario: High-speed PCIe Gen 4 switch with multiple upstream/downstream ports requiring synchronized, low-jitter clocks. IC Role / Device Role / Timing Role: Quad clock generator providing four independent 100 MHz HCSL clocks with <0.45 ps RMS jitter and PCIe Gen 4 common clock compliance. Use Value: Eliminates four discrete oscillators; enables single-device timing for multi-lane PCIe topology with guaranteed jitter margin.	Use Scenario: Carrier-grade line card supporting 10G/25G Ethernet, CPRI, and SyncE with strict phase noise and wander requirements. IC Role / Device Role / Timing Role: Configurable clock buffer/generator delivering 156.25 MHz LVDS and 10 MHz CMOS outputs from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board space; supports holdover mode via LOS alarm during reference failure.
FPGA-Based Broadcast Video System	DSLAM / MSAN Jitter Attenuation
Use Scenario: SMPTE ST 2110 video processing platform using Xilinx Ultrascale+ FPGA requiring precise 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks. IC Role / Device Role / Timing Role: Any-frequency clock generator synthesizing three non-integer-related video clocks from one 27 MHz crystal with <0.7 ps RMS jitter. Use Value: Replaces three separate VCXOs; ensures sub-picosecond jitter alignment critical for multi-channel video synchronization.	Use Scenario: DSL access multiplexer requiring ultra-low broadband jitter (<2 ps RMS, 10 kHz–400 kHz) for ADSL2+/VDSL2 line cards. IC Role / Device Role / Timing Role: Jitter-attenuating clock buffer operating in 475 kHz loop bandwidth mode with 70.656 MHz input/output. Use Value: Meets ITU-T G.992.3/G.993.2 spectral mask requirements without external analog PLL components.

PCI Express Switch Fabric

Telecom Line Card Timing

Use Scenario: High-speed PCIe Gen 4 switch with multiple upstream/downstream ports requiring synchronized, low-jitter clocks.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent 100 MHz HCSL clocks with <0.45 ps RMS jitter and PCIe Gen 4 common clock compliance.

Use Value: Eliminates four discrete oscillators; enables single-device timing for multi-lane PCIe topology with guaranteed jitter margin.

Use Scenario: Carrier-grade line card supporting 10G/25G Ethernet, CPRI, and SyncE with strict phase noise and wander requirements.

IC Role / Device Role / Timing Role: Configurable clock buffer/generator delivering 156.25 MHz LVDS and 10 MHz CMOS outputs from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and board space; supports holdover mode via LOS alarm during reference failure.

FPGA-Based Broadcast Video System

DSLAM / MSAN Jitter Attenuation

Use Scenario: SMPTE ST 2110 video processing platform using Xilinx Ultrascale+ FPGA requiring precise 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks.

IC Role / Device Role / Timing Role: Any-frequency clock generator synthesizing three non-integer-related video clocks from one 27 MHz crystal with <0.7 ps RMS jitter.

Use Value: Replaces three separate VCXOs; ensures sub-picosecond jitter alignment critical for multi-channel video synchronization.

Use Scenario: DSL access multiplexer requiring ultra-low broadband jitter (<2 ps RMS, 10 kHz–400 kHz) for ADSL2+/VDSL2 line cards.

IC Role / Device Role / Timing Role: Jitter-attenuating clock buffer operating in 475 kHz loop bandwidth mode with 70.656 MHz input/output.

Use Value: Meets ITU-T G.992.3/G.993.2 spectral mask requirements without external analog PLL components.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-D08629-GM	Higher integration: 8 outputs, integrated EEPROM, enhanced jitter performance (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at high-end data converters and 5G wireless infrastructure where deterministic delay and ultra-low jitter are mandatory	Choose Si5345A-D08629-GM for JESD204B-compliant systems or when >4 outputs and onboard configuration storage are required
ICS8430I-01T	Fixed-function 4-output LVDS clock generator; no fractional synthesis, no spread spectrum, no user-configurable control pins	Suitable only for static, low-cost clock fanout where all outputs share same frequency and format	Choose ICS8430I-01T only for simple, unchanging clock distribution with no frequency flexibility or jitter attenuation needs

Compared with Si5345A-D08629-GM and ICS8430I-01T, SI5335D-B04730-GMR delivers optimal balance of field-programmable flexibility, PCIe/DSL jitter compliance, and cost-effective quad-output capability - making it ideal for mid-tier telecom, enterprise switch, and FPGA timing applications where reconfigurability and mixed-format support are essential.

Availability

SI5335D-B04730-GMR is available at Aetrix Electronics and suitable for PCIe switch design, telecom line card development, broadcast video timing, and FPGA clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5335D-B04730-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad manufacturing scale and automotive-grade reliability.

The Si5335 product line was designed specifically for high-flexibility, multi-protocol timing in networking, computing, and communications equipment - enabling consolidation of discrete clock sources into a single, software-configurable IC.

FAQ

What is the primary function of the SI5335D-B04730-GMR?

The SI5335D-B04730-GMR is a quad-output, web-customizable clock generator/buffer IC that synthesizes up to four independent, non-integer-related frequencies (1–350 MHz) with zero ppm frequency error using Skyworks' MultiSynth fractional divider technology. It replaces multiple oscillators and clock ICs in complex timing architectures while maintaining PCIe Gen 1–4 and DSL jitter compliance.

Does the SI5335D-B04730-GMR support spread spectrum clocking?

Yes, the SI5335D-B04730-GMR supports spread spectrum clocking via the SSENB control pin, with default settings of –0.5% down-spread modulation at 31.5 kHz - meeting PCI-SIG spread spectrum requirements for EMI reduction in host systems. The feature is configurable through ClockBuilder Pro and requires no external components.

How many output formats does the SI5335D-B04730-GMR support per bank?

The SI5335D-B04730-GMR supports LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL output formats across its four banks. Each bank can be independently configured for format, voltage (1.5/1.8/2.5/3.3 V), drive strength, and enable state - enabling mixed-signal interface support on a single device.

What is the significance of the "B04730" suffix in SI5335D-B04730-GMR?

The "B04730" suffix identifies a factory-programmed configuration variant of the SI5335D base part. It specifies pre-defined output frequencies, formats, voltage levels, and control pin assignments generated via Skyworks' ClockBuilder Pro tool - enabling drop-in deployment without post-manufacture programming.

Can the SI5335D-B04730-GMR operate without an external crystal?

Yes, the SI5335D-B04730-GMR can operate without an external crystal by accepting a single-ended (10–200 MHz) or differential (10–350 MHz) clock signal on its XA/XB input pins. When used in PLL bypass (buffer) mode, it achieves <4 ns propagation delay and 12 mA core current - ideal for low-power clock distribution.

SI5335D-B04730-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5335D-B04730-GMR FAQ

1.How can I place an order for SI5335D-B04730-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5335D-B04730-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5335D-B04730-GMR reliable?

The price and inventory of SI5335D-B04730-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5335D-B04730-GMR is usually 5 days.

3.What payment methods are accepted for SI5335D-B04730-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5335D-B04730-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5335D-B04730-GMR?

SI5335D-B04730-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5335D-B04730-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5335D-B04730-GMR?

For technical support, including SI5335D-B04730-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5335D-B04730-GMR requirements.

6.How does Aetrix verify that SI5335D-B04730-GMR is sourced from the original manufacturer or authorized distributors?

All SI5335D-B04730-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5335D-B04730-GMR meets industry standards.

7.What is the process for return or replacement of SI5335D-B04730-GMR?

All SI5335D-B04730-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5335D-B04730-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5335D-B04730-GMR part is unused and in its original packaging.

Return procedure for SI5335D-B04730-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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