Skyworks Solutions Inc. SI5335D-B04798-GMR

Overview

SI5335D-B04798-GMR from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC supporting four independent non-integer-related frequencies up to 350 MHz. It features MultiSynth fractional synthesis with 0 ppm frequency error, PCIe Gen 1–4 common clock compliance, and dual selectable PLL loop bandwidths (1.6 MHz / 475 kHz). Used in high-speed serial interface timing for PCIe switch cards and FPGA-based telecom line cards.

For engineers reviewing the SI5335D-B04798-GMR datasheet, SI5335D-B04798-GMR pinout, SI5335D-B04798-GMR application, or SI5335D-B04798-GMR equivalent, key selection factors include its 0.7 ps RMS phase jitter (12 kHz–20 MHz), configurable output formats (LVPECL/LVDS/HCSL/CMOS/SSTL), loss-of-signal alarm, and support for three pin-selectable device configurations - critical for multi-standard system clocking.

Technical Context

The SI5335D-B04798-GMR implements a single high-performance PLL with patented MultiSynth fractional-N dividers per output bank, enabling independent synthesis of four frequencies without integer constraints. Input reference flexibility includes 25/27 MHz crystal, CMOS (10–200 MHz), or differential (10–350 MHz) sources.

Its architecture supports both clock generator mode (PLL active, 45 mA core current) and low-power buffer mode (PLL bypass, 12 mA core current), with programmable output voltage per driver (1.5/1.8/2.5/3.3 V) and five user-assignable control pins (e.g., SSENB, FS[1:0], RESET, OEB). Loss-of-signal detection activates within 2.6–5 µs on CLKIN failure.

Key Specifications

Pinout & Package

SI5335D-B04798-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5335 top-view layout, with dedicated input (XA/CLKIN, XB/CLKINB), four output banks (CLK0A/B through CLK3A/B), supply rails (VDD, VDDO0–VDDO3), control pins (P1–P6), LOS alarm, and reserved ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5341-A02571-GM and ICS8430I-01LG, SI5335D-B04798-GMR uniquely balances 4-output flexibility, PCIe Gen 4 compliance, and field-programmable frequency synthesis in a compact 24-QFN - making it optimal for mid-complexity telecom and compute platforms where pin count and configurability are constrained.

Availability

SI5335D-B04798-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, FPGA clocking, telecom line card synchronization, and DSLAM jitter attenuation requiring stable component supply and factory-configurable timing solutions.

Supply support for SI5335D-B04798-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly configurable, any-frequency clock generation for high-speed serial interfaces - designed specifically to replace multiple discrete oscillators and buffers in PCIe, Ethernet, and telecom infrastructure.

FAQ

What is the primary function of the SI5335D-B04798-GMR?

The SI5335D-B04798-GMR is a quad-output, web-customizable clock generator/buffer IC that synthesizes four independent, non-integer-related frequencies up to 350 MHz with zero ppm frequency error. It serves as a timing hub in systems requiring PCIe Gen 1–4 compliance, jitter attenuation, and flexible output formatting - all within a single 24-QFN package. Its MultiSynth technology enables replacement of multiple discrete clock sources.

Does the SI5335D-B04798-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04798-GMR meets PCIe Gen 4 common clock jitter specifications, delivering ≤0.45 ps RMS phase jitter (12 kHz–20 MHz) when configured with 1.6 MHz PLL loop bandwidth and differential outputs (e.g., HCSL). It is explicitly validated for PCIe Gen 4 in Skyworks' documentation and supports spread spectrum for EMI reduction - critical for high-density server and switch designs.

How many output configurations can be stored and selected on the SI5335D-B04798-GMR?

The SI5335D-B04798-GMR supports three independent, pin-selectable device configurations. These are programmed via FS[1:0] control pins and allow hardware-switched selection between distinct frequency plans, output formats, and voltage settings - enabling one device to serve multiple operational modes (e.g., test vs. production, legacy vs. upgraded link speed) without firmware intervention.

What is the role of the LOS pin on the SI5335D-B04798-GMR?

The LOS (Loss-of-Signal) pin on the SI5335D-B04798-GMR is an open-drain alarm output that asserts within 2.6–5 µs of detecting failure on the primary reference input (XA/CLKIN or XB/CLKINB). It provides real-time fault indication to system supervisors or FPGAs, enabling rapid failover or safe shutdown - essential for carrier-grade telecom and industrial systems requiring high reliability.

Can the SI5335D-B04798-GMR operate as a pure clock buffer without PLL synthesis?

Yes, the SI5335D-B04798-GMR supports PLL bypass (buffer) mode, where input clock signals pass directly to outputs with minimal added jitter (2.5–4 ns propagation delay). In this mode, core supply current drops to 12 mA, and the device functions as a level-translating, format-converting buffer - ideal for cleaning or distributing existing references while retaining full output configurability (voltage, format, enable control).