Skyworks Solutions Inc. SI5335D-B04819-GMR

Overview

SI5335D-B04819-GMR from Skyworks Solutions is a web-customizable quad clock generator/buffer IC with four independent, non-integer-related output frequencies up to 350 MHz, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL/CML output formats in a 4 × 4 mm 24-QFN package. It serves as a single-chip replacement for multiple oscillators and clock ICs in high-speed serial interface timing systems.

For engineers reviewing the SI5335D-B04819-GMR datasheet, SI5335D-B04819-GMR pinout, SI5335D-B04819-GMR application, or SI5335D-B04819-GMR equivalent, key selection considerations include its MultiSynth fractional synthesis architecture, dual PLL loop bandwidth options (1.6 MHz / 475 kHz), loss-of-signal alarm, five user-assignable control pins, and factory-programmable configuration via ClockBuilder Pro.

Technical Context

The SI5335D-B04819-GMR implements Skyworks' patented MultiSynth fractional divider technology across four independent synthesis paths, each feeding one of four output banks. Each bank supports either one differential pair or two single-ended outputs, with per-driver voltage selection (1.5/1.8/2.5/3.3 V) and format flexibility (LVPECL to CMOS).

It features a dual-loop PLL architecture with selectable bandwidths (1.6 MHz for PCIe jitter attenuation, 475 kHz for DSL applications), pin-selectable device configurations (up to three), and configurable input support including 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), and differential (10–350 MHz) references.

Key Specifications

Pinout & Package

SI5335D-B04819-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments follow the standard Si5335 top-view layout and are validated per Skyworks Rev. 1.4 datasheet (pages 2, 10, 38–40).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5345B-D06894-GM and ICS8430I-01T, the SI5335D-B04819-GMR uniquely balances four-output synthesis flexibility, PCIe Gen 4 readiness, and compact 4 × 4 mm footprint-making it optimal for space-constrained, multi-standard timing in servers, switches, and telecom edge equipment.

Availability

SI5335D-B04819-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, 10 GbE switch clocking, and broadcast video synchronization requiring stable component supply, long-term lifecycle assurance, and factory-programmed configuration traceability.

Supply support for SI5335D-B04819-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5335 product line delivers highly configurable, any-frequency clock generation for high-speed serial interfaces-including PCIe, Ethernet, and telecom standards-enabling system-level timing consolidation and reduced design risk.

FAQ

What is the primary function of the SI5335D-B04819-GMR?

The SI5335D-B04819-GMR is a quad-output, web-customizable clock generator/buffer IC that synthesizes four independent, non-integer-related frequencies up to 350 MHz using Skyworks' MultiSynth fractional divider technology. Its primary function is to replace multiple discrete oscillators and clock ICs in high-speed digital systems while maintaining sub-1 ps RMS phase jitter and PCIe Gen 1–4 compliance.

Does the SI5335D-B04819-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5335D-B04819-GMR meets PCIe Gen 4 common clock jitter specifications with ≤0.45 ps RMS (10 kHz–50 MHz) when configured in 1.6 MHz PLL loop bandwidth mode and using HCSL outputs at 100 MHz. It is explicitly listed as PCIe Gen 4 common clock compliant in Skyworks documentation (Rev. 1.4, page 1).

How many output configurations can be stored and selected on the SI5335D-B04819-GMR?

The SI5335D-B04819-GMR supports up to three independent, pin-selectable device configurations. These are selected via the FS1 and FS0 control pins (P2 and P3), allowing hardware-based switching between pre-programmed frequency plans, output formats, and enable states without reprogramming.

What input reference options does the SI5335D-B04819-GMR accept?

The SI5335D-B04819-GMR accepts multiple input references: 25 MHz or 27 MHz fundamental-mode crystals (internal 18 pF load), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), and differential (LVDS/LVPECL/HCSL/CML, 10–350 MHz). Input flexibility enables use with existing system clocks or low-cost crystals.

Is the SI5335D-B04819-GMR pin-compatible with other Si5335 variants?

Yes, all Si5335 family members-including SI5335D-B04819-GMR-are pin-compatible within the 24-QFN package. Differences lie in factory-programmed configuration (frequency plans, output formats, control pin functions), not pinout or electrical interface. This allows design reuse across variants with only firmware/configuration changes.