Skyworks Solutions Inc. SI5335D-B05721-GM

Overview

SI5335D-B05721-GM from Skyworks Solutions is a web-customizable, quad-output clock generator/buffer IC supporting four non-integer-related frequencies up to 350 MHz, with 0 ppm synthesis error via MultiSynth fractional divider technology, 0.7 ps RMS phase jitter, PCIe Gen 1–4 common clock compliance, and operation across –40 to +85 °C for telecom line cards and FPGA clocking.

For engineers reviewing the SI5335D-B05721-GM datasheet, SI5335D-B05721-GM pinout, SI5335D-B05721-GM application, or SI5335D-B05721-GM equivalent, key selection criteria include differential output format support (LVPECL/LVDS/HCSL/CML), dual PLL loop bandwidth options (1.6 MHz / 475 kHz), loss-of-signal alarm, and pin-selectable frequency plans for multi-configuration system design.

Technical Context

The SI5335D-B05721-GM integrates a single high-performance PLL with patented MultiSynth fractional-N synthesis per output bank, enabling independent frequency generation without integer constraints. It supports both clock generator mode (45 mA core current) and low-power buffer mode (12 mA core current) with PLL bypass capability.

Input flexibility includes 25/27 MHz crystal, CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) references. Output drivers are independently configurable per bank for voltage (1.5/1.8/2.5/3.3 V), format (LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL), and enable control, with five user-assignable pins for SSENB, RESET, OEB, and FS[1:0].

Key Specifications

Pinout & Package

SI5335D-B05721-GM is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.4 datasheet, with dedicated input (XA/CLKIN, XB/CLKINB), four differential output banks (CLK0A/B through CLK3A/B), supply rails (VDD, VDDO0–VDDO3), control pins (P1–P6), LOS alarm, and ground connections.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5341-B-GM and ICS8430I-01LG, the SI5335D-B05721-GM uniquely balances pin-selectable reconfigurability, 0 ppm synthesis accuracy, and 4×4 mm footprint - making it optimal for space-constrained, multi-mode telecom and computing platforms requiring field-upgradable timing.

Availability

SI5335D-B05721-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, DSLAM line cards, and FPGA-based broadcast video systems requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.

Supply support for SI5335D-B05721-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and mobile markets.

The Si5335 family was designed as a highly flexible, web-customizable clock generator/buffer platform targeting multi-protocol timing consolidation in networking, computing, and telecom equipment - replacing discrete oscillators and clock trees with a single programmable IC.

FAQ

What is the primary function of the SI5335D-B05721-GM?

The SI5335D-B05721-GM is a quad-output, web-customizable clock generator/buffer IC that synthesizes four independent, non-integer-related frequencies up to 350 MHz with 0 ppm error using Skyworks' MultiSynth technology. It operates as either a full-featured clock generator or a low-power buffer, supporting PCIe Gen 1–4, DSL, and broadcast video timing requirements. Its pin-selectable configurations and flexible I/O make it ideal for consolidating multiple timing sources into a single device.

Does the SI5335D-B05721-GM support PCIe Gen 4 timing specifications?

Yes, the SI5335D-B05721-GM is PCIe Gen 4 common clock compliant, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) under specified test conditions (100 MHz HCSL outputs, 1.6 MHz loop bandwidth). This meets the PCI-SIG Base Specification 4.0 rev. 0.5 requirement for common clock architectures, validated using the Intel Clock Jitter Tool and Skyworks' PCIe Clock Jitter Tool.

How many independent output voltage supplies does the SI5335D-B05721-GM support?

The SI5335D-B05721-GM supports four independent output buffer supply rails - VDDO0, VDDO1, VDDO2, and VDDO3 - each configurable from 1.4 V to 3.63 V. This enables simultaneous interfacing with mixed-voltage loads (e.g., 1.8 V FPGA I/O banks and 3.3 V legacy peripherals) without external level shifters, preserving signal integrity and reducing BOM count.

Can the SI5335D-B05721-GM operate without an external crystal?

Yes, the SI5335D-B05721-GM accepts multiple reference inputs: external 25/27 MHz crystals, or AC-coupled CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), or differential (10–350 MHz) clock signals. Crystal operation uses on-chip 18 pF load capacitance; for non-crystal references, external termination (e.g., 100 Ω for differential) is required per Skyworks' layout guidelines.

What is the significance of the "B05721" suffix in SI5335D-B05721-GM?

The "B05721" suffix denotes a factory-programmed configuration generated via Skyworks' ClockBuilder Pro web utility. It specifies a unique combination of output frequencies, formats, voltages, and pin-control assignments (e.g., P1–P6 functions, FS[1:0] mapping). This pre-programmed variant eliminates post-manufacturing configuration steps, ensuring immediate plug-and-play operation in target systems.