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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B01086-GMR

Name: SI5338A-B01086-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B01086-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B01086-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B01086-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338A-B01086-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.

For engineers reviewing the SI5338A-B01086-GMR datasheet, SI5338A-B01086-GMR pinout, SI5338A-B01086-GMR application, or SI5338A-B01086-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), loss-of-lock/loss-of-signal alarms, and I²C/SMBus programmability.

Technical Context

The SI5338A-B01086-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving one output channel. This enables true zero-ppm frequency accuracy across all outputs without requiring external loop filters.

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage rail assignment (VDDO0–VDDO3), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). Input flexibility includes differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and crystal (8–30 MHz) references.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements.
Output Frequency Range	0.16–710 MHz per channel; supports integer/fractional synthesis with ≤1 ppb resolution.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Output Format Flexibility	Four differential outputs (LVPECL/LVDS/HCSL/CML) or eight single-ended (CMOS/SSTL/HSTL), or mixed.
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3.
Operating Temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card applications.

Pinout & Package

SI5338A-B01086-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family: six inputs (IN1–IN6), four differential output pairs (CLK0A/B through CLK3A/B), four VDDOx rails, dual VDD core supplies, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination.
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; DC-coupled with internal bias.
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent outputs; each pair supports LVPECL/LVDS/HCSL/CML with dedicated VDDOx supply.
VDDO0–VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V assignment per output pair; enables mixed-voltage system interfacing.
VDD (Pins 9,10)	Core supply	Single 1.8/2.5/3.3 V supply for PLL, logic, and memory; PSRR optimized for noise immunity.
SCL/SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro configuration and runtime reprogramming.
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events.

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent output channels each synthesize any frequency from 0.16 to 710 MHz with 0 ppm error and ≤1 ppb resolution.
PCIe Gen 1–4 Compliance	Fully compliant with PCIe Gen 1/2/3 Common Clock and Gen 3 Separate Reference No Spread (SRNS); validated per Intel Clock Jitter Tool v1.6.4.
Programmable Spread Spectrum	Per-output SSC with adjustable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down/up/center); reduces EMI in dense PCB layouts.
Glitchless Frequency Adjustment	Real-time frequency increment/decrement via pins or I²C at 1 ppm steps without output interruption or phase discontinuity.
Independent Phase Control	±45 ns programmable phase offset per output with <20 ps step resolution; enables precise timing alignment in multi-clock domain systems.
Flexible Input Architecture	Supports crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references - no external oscillator required.

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 System Clocking
Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Quad clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz clocks with sub-1 ps jitter for SerDes lanes and control logic. Use Value: Eliminates four discrete oscillators; enables jitter-constrained PCIe Gen 4 link training and deterministic packet forwarding latency.	Use Scenario: Server motherboard with CPU, GPU, and NVMe SSDs sharing a common reference clock under PCIe Gen 3 SRNS or Gen 4 common clock architecture. IC Role / Device Role / Timing Role: Primary clock source delivering 100 MHz HCSL clocks to root complex and endpoints with 0.11–0.45 ps RMS jitter per PCIe spec. Use Value: Meets strict PCIe Gen 4 total jitter limits (≤33.6 ps pk-pk) while supporting dynamic frequency scaling and spread spectrum for EMI reduction.
Broadcast Video/Audio Synchronization	FPGA & Processor Clock Distribution
Use Scenario: SMPTE ST 2082/2081 video over IP infrastructure requiring frame-accurate genlock across encoder, decoder, and transport modules. IC Role / Device Role / Timing Role: Master timing IC generating 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with programmable phase offsets for pixel-level alignment. Use Value: Achieves <20 ps phase step resolution and <100 ps output-to-output skew, enabling sub-sample video synchronization across distributed nodes.	Use Scenario: Heterogeneous compute platform with ARM SoC, Xilinx Zynq MPSoC, and high-speed ADC/DAC interfaces needing isolated, low-jitter clocks. IC Role / Device Role / Timing Role: Centralized clock hub supplying 50 MHz system clock, 200 MHz DDR interface clock, 1 GHz transceiver reference, and 10 MHz debug clock. Use Value: Independent VDDOx rails allow simultaneous 1.8 V (FPGA I/O), 2.5 V (DDR), and 3.3 V (analog subsystem) clock distribution without level shifters.

Ethernet Switch/Router Timing

PCIe Gen 3/4 System Clocking

Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors.

IC Role / Device Role / Timing Role: Quad clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz clocks with sub-1 ps jitter for SerDes lanes and control logic.

Use Value: Eliminates four discrete oscillators; enables jitter-constrained PCIe Gen 4 link training and deterministic packet forwarding latency.

Use Scenario: Server motherboard with CPU, GPU, and NVMe SSDs sharing a common reference clock under PCIe Gen 3 SRNS or Gen 4 common clock architecture.

IC Role / Device Role / Timing Role: Primary clock source delivering 100 MHz HCSL clocks to root complex and endpoints with 0.11–0.45 ps RMS jitter per PCIe spec.

Use Value: Meets strict PCIe Gen 4 total jitter limits (≤33.6 ps pk-pk) while supporting dynamic frequency scaling and spread spectrum for EMI reduction.

Broadcast Video/Audio Synchronization

FPGA & Processor Clock Distribution

Use Scenario: SMPTE ST 2082/2081 video over IP infrastructure requiring frame-accurate genlock across encoder, decoder, and transport modules.

IC Role / Device Role / Timing Role: Master timing IC generating 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with programmable phase offsets for pixel-level alignment.

Use Value: Achieves <20 ps phase step resolution and <100 ps output-to-output skew, enabling sub-sample video synchronization across distributed nodes.

Use Scenario: Heterogeneous compute platform with ARM SoC, Xilinx Zynq MPSoC, and high-speed ADC/DAC interfaces needing isolated, low-jitter clocks.

IC Role / Device Role / Timing Role: Centralized clock hub supplying 50 MHz system clock, 200 MHz DDR interface clock, 1 GHz transceiver reference, and 10 MHz debug clock.

Use Value: Independent VDDOx rails allow simultaneous 1.8 V (FPGA I/O), 2.5 V (DDR), and 3.3 V (analog subsystem) clock distribution without level shifters.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B01101-GM	Same Si5338A die; factory-programmed for different default frequency configuration (100/125/156.25/250 MHz) and I²C address.	Pre-configured for data center networking; lacks user-defined spread-spectrum settings out-of-box.	Select when pre-validated PCIe timing is prioritized over field reprogrammability.
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C, no MultiSynth™); 0.9 ps RMS jitter; 100/125/156.25/200 MHz only.	Targeted at cost-sensitive, non-reconfigurable applications; no phase/frequency adjustment or crystal input support.	Select only for static clock trees where design changes are prohibited post-BOM freeze.

Compared with SI5338A-B01086-GMR, Si5338A-B01101-GM offers faster time-to-operate but sacrifices field configurability, while ICS8430I-01T provides lower unit cost at the expense of frequency flexibility, jitter performance, and input reference options.

Availability

SI5338A-B01086-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 3/4 system clocking, and broadcast video/audio synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B01086-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers high-precision, software-programmable clock generation for systems demanding ultra-low jitter, multi-format outputs, and flexible reference inputs - targeting data center, telecom, and broadcast equipment designers.

FAQ

What is the primary function of the SI5338A-B01086-GMR?

The SI5338A-B01086-GMR is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference (crystal or external clock). It replaces up to four discrete oscillators in applications like PCIe Gen 4 and 10 GbE, delivering frequencies from 0.16 to 710 MHz with 0.7 ps RMS typical phase jitter and zero-ppm accuracy via MultiSynth™ technology.

Does the SI5338A-B01086-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338A-B01086-GMR meets PCIe Gen 4 common clock specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz band) and supports Gen 3 Separate Reference No Spread (SRNS) mode. It is validated using the Skyworks PCIe Clock Jitter Tool and complies with Intel Clock Jitter Tool v1.6.4 measurement methodology for 100 MHz HCSL outputs.

Can the SI5338A-B01086-GMR generate different output voltages on each channel?

Yes, the SI5338A-B01086-GMR supports independent output buffer supply rails (VDDO0–VDDO3), allowing each of its four output pairs to be configured for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components - such as 1.8 V FPGAs, 2.5 V DDR controllers, and 3.3 V legacy peripherals - without external level shifters.

How is the SI5338A-B01086-GMR programmed and configured?

The SI5338A-B01086-GMR is programmed via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software. This GUI tool enables full register configuration, frequency synthesis setup, spread-spectrum parameters, phase offsets, and output format selection. Configuration can be stored in on-chip OTP memory for autonomous startup or updated dynamically in-system.

What package type and footprint does the SI5338A-B01086-GMR use?

The SI5338A-B01086-GMR uses a 24-lead QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad. It follows JEDEC MO-220WWGG variant outline and requires standard reflow profiles (J-STD-020, peak 260 °C). The pinout is identical across the Si5338 family, enabling drop-in compatibility within the same package variant.

SI5338A-B01086-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B01086-GMR FAQ

1.How can I place an order for SI5338A-B01086-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B01086-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B01086-GMR reliable?

The price and inventory of SI5338A-B01086-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B01086-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B01086-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B01086-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B01086-GMR?

SI5338A-B01086-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B01086-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B01086-GMR?

For technical support, including SI5338A-B01086-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B01086-GMR requirements.

6.How does Aetrix verify that SI5338A-B01086-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B01086-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B01086-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B01086-GMR?

All SI5338A-B01086-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B01086-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B01086-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B01086-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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