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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B01223-GM

Name: SI5338A-B01223-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B01223-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B01223-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B01223-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338A-B01223-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, supporting 0.16–710 MHz output frequencies and PCIe Gen 1–4 compliance - deployed in FPGA clocking, Ethernet switch timing, and broadcast video systems.

For engineers reviewing the SI5338A-B01223-GM datasheet, SI5338A-B01223-GM pinout, SI5338A-B01223-GM application, or SI5338A-B01223-GM equivalent, key selection considerations include its 24-QFN package, independent per-output voltage control (1.5–3.3 V), ±20 ps phase step resolution, spread-spectrum capability (0.5–5.0% down-spread), and external crystal input support (8–30 MHz).

Technical Context

The SI5338A-B01223-GM integrates a two-stage PLL architecture: a high-stability reference stage (with programmable R-divider) feeding a fractional-N MultiSynth™ synthesis stage per output, enabling independent integer/fractional frequency generation with <1 ppb resolution. Its core operates from 1.8/2.5/3.3 V and achieves 25 ms PLL lock time.

Each of the four differential output drivers supports configurable format, voltage, slew rate, and termination; outputs can be enabled/disabled individually via OEB pins or I²C. The device includes loss-of-signal and loss-of-lock alarms, programmable initial phase offset (±45 ns), and glitchless frequency increment/decrement (1 ppm steps) controlled by dedicated pins or I²C.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	Four independently configurable differential outputs (CLK0A/B through CLK3A/B), supporting up to eight single-ended clocks via driver reconfiguration
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and Gen 4 common-clock jitter requirements
Frequency Range	0.16–710 MHz per output, with ≥2 unique frequencies >350 MHz simultaneously (Fvco/4 and Fvco/6)
Input Reference Support	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V (±10%); Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line-card environments

Pinout & Package

SI5338A-B01223-GM is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5338 family; this variant uses all standard pin functions without customization.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; internally biased with 20 kΩ pull-up/down
CLK0A/CLK0B – CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL, LVDS, HCSL, CML, or SSTL/HSTL with per-driver VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output pair - enables mixed-voltage system interfacing
SCL/SDA	I²C interface	Standard SMBus-compatible serial bus (up to 400 kHz) for configuration, status readback, and dynamic tuning
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-signal, loss-of-lock, or NVM error; active-low assertion
OEB/PINC/FINC	Control pins	Hardware-enable/disable outputs (OEB); pin-controlled frequency/phase increment/decrement (PINC/FINC)

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Enables true zero-ppm accuracy on all four outputs simultaneously, eliminating need for multiple crystals or oscillators
Independent output voltage per driver	Allows direct interfacing with mixed-voltage SoCs, FPGAs, and SerDes without level-shifting components
Glitchless frequency adjustment	1 ppm step size with hardware pin control (PINC/FINC) enables real-time clock tuning without output interruption
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) reduces EMI in dense PCB layouts
PCIe Gen 1–4 compliance	Validated for Common Clock and Gen 3 SRNS modes; meets Intel's jitter specifications at 100 MHz HCSL
Zero-delay mode support	External feedback path enables synchronous clock distribution with minimal propagation delay skew

Applications

Ethernet Switch Timing	PCIe Gen 4 System Clocking
Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Primary clock generator providing four independent, low-jitter clocks (125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz) with matched phase alignment. Use Value: Eliminates inter-chip skew and jitter accumulation; enables deterministic latency across multi-lane SerDes links.	Use Scenario: Server motherboard with dual CPU sockets and PCIe Gen 4 x16 slots, requiring compliant common-clock reference for root complex and endpoint devices. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz HCSL clocks with ≤0.45 ps RMS jitter (Gen 4 spec) and loss-of-lock monitoring. Use Value: Ensures PCIe link training success and sustained Gen 4 data rates; avoids retries or downgrades due to jitter-induced bit errors.
Broadcast Video Synchronization	FPGA-Based Signal Processing
Use Scenario: SMPTE ST 2059-2–compliant video router using PTP grandmaster timing, requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact broadcast-standard frequencies from a single 25 MHz crystal reference. Use Value: Replaces three discrete oscillators; maintains frame-accurate sync across SDI transmitters, color correctors, and frame synchronizers.	Use Scenario: High-throughput radar processing unit with Xilinx Kintex Ultrascale+ FPGA, needing multiple domain clocks (100 MHz logic, 250 MHz ADC interface, 500 MHz DDR4, 1 GHz GTY transceivers). IC Role / Device Role / Timing Role: Configurable clock hub providing four precisely phased, format-matched clocks with independent voltage control per domain. Use Value: Reduces BOM count and layout area; simplifies power sequencing and eliminates cross-domain jitter coupling.

Ethernet Switch Timing

PCIe Gen 4 System Clocking

Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent, low-jitter clocks (125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz) with matched phase alignment.

Use Value: Eliminates inter-chip skew and jitter accumulation; enables deterministic latency across multi-lane SerDes links.

Use Scenario: Server motherboard with dual CPU sockets and PCIe Gen 4 x16 slots, requiring compliant common-clock reference for root complex and endpoint devices.

IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz HCSL clocks with ≤0.45 ps RMS jitter (Gen 4 spec) and loss-of-lock monitoring.

Use Value: Ensures PCIe link training success and sustained Gen 4 data rates; avoids retries or downgrades due to jitter-induced bit errors.

Broadcast Video Synchronization

FPGA-Based Signal Processing

Use Scenario: SMPTE ST 2059-2–compliant video router using PTP grandmaster timing, requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact broadcast-standard frequencies from a single 25 MHz crystal reference.

Use Value: Replaces three discrete oscillators; maintains frame-accurate sync across SDI transmitters, color correctors, and frame synchronizers.

Use Scenario: High-throughput radar processing unit with Xilinx Kintex Ultrascale+ FPGA, needing multiple domain clocks (100 MHz logic, 250 MHz ADC interface, 500 MHz DDR4, 1 GHz GTY transceivers).

IC Role / Device Role / Timing Role: Configurable clock hub providing four precisely phased, format-matched clocks with independent voltage control per domain.

Use Value: Reduces BOM count and layout area; simplifies power sequencing and eliminates cross-domain jitter coupling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B01222-GM	Same silicon, identical electrical specs; differs only in factory-programmed NVM configuration (different default frequency map)	No functional difference in supported use cases; requires reprogramming via ClockBuilder Pro for alternate output profiles	Select when preconfigured startup frequencies match legacy design requirements
LMK04832ISQE/NOPB	Two PLLs (not four independent MultiSynths); higher power (120 mA vs. 45 mA typ); larger 48-QFN package	Better suited for ultra-low-jitter (<0.1 ps) RF sampling clocks; less flexible for multi-frequency, multi-format routing	Choose for sub-0.2 ps jitter-critical instrumentation or wireless infrastructure where power and size are secondary

Compared with SI5338A-B01222-GM, the SI5338A-B01223-GM offers identical performance but different factory NVM settings; versus LMK04832ISQE/NOPB, it trades absolute jitter floor for lower power, smaller footprint, and superior per-output configurability - making it optimal for space-constrained, multi-protocol embedded systems.

Availability

SI5338A-B01223-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 server platforms, and broadcast video synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B01223-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for communications, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for systems demanding multi-frequency, multi-format timing - designed specifically for FPGA, processor, and high-speed serial interface clocking in networking, computing, and broadcast equipment.

FAQ

What is the primary function of the SI5338A-B01223-GM in a timing architecture?

The SI5338A-B01223-GM serves as a quad-output, any-frequency clock generator that replaces up to four discrete oscillators or crystal-based clock sources. It synthesizes four independent, low-jitter output clocks (0.16–710 MHz) from a single reference input using Skyworks' patented MultiSynth™ technology. Its role is to provide precise, configurable timing signals for FPGAs, processors, SerDes lanes, and network PHYs - all within a single 4×4 mm QFN package. SI5338A-B01223-GM enables deterministic phase relationships and eliminates board-level clock skew.

Does the SI5338A-B01223-GM support PCIe Gen 4 common-clock compliance?

Yes, the SI5338A-B01223-GM is explicitly validated for PCIe Gen 4 common-clock operation, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) at 100 MHz HCSL output under specified test conditions. This meets the PCI-SIG Gen 4 specification requirement. The device achieves this via optimized PLL loop bandwidth (2–4 MHz), low-noise VCO design, and differential output architecture. SI5338A-B01223-GM also supports Gen 1/2/3 and Gen 3 SRNS modes, making it backward-compatible across PCIe generations.

Can the SI5338A-B01223-GM generate different output voltages on each channel?

Yes, the SI5338A-B01223-GM provides independent output buffer supply pins (VDDO0–VDDO3), allowing each of the four differential output pairs to operate at a different voltage: 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components - for example, driving a 1.8 V FPGA I/O bank, a 2.5 V SerDes receiver, a 3.3 V microcontroller, and a 1.5 V memory controller - without external level shifters. SI5338A-B01223-GM's per-channel voltage control is configured at power-up via NVM or dynamically via I²C.

How is the SI5338A-B01223-GM programmed and configured?

The SI5338A-B01223-GM is programmed via an I²C/SMBus-compatible serial interface (SCL/SDA pins) operating up to 400 kHz. Configuration is simplified using Skyworks' ClockBuilder Pro software, which generates custom .cbs files for frequency, format, voltage, phase, and spread-spectrum settings. These configurations can be written to the device's one-time-programmable (OTP) NVM or loaded into volatile RAM at boot. SI5338A-B01223-GM also supports pin-controlled frequency/phase adjustments (PINC/FINC) and hardware output enable (OEB) for runtime tuning without host intervention.

What package type and thermal characteristics does the SI5338A-B01223-GM have?

The SI5338A-B01223-GM uses a 24-lead QFN package measuring 4 mm × 4 mm with 0.5 mm pitch and an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load across –40 °C to +85 °C ambient. The exposed pad must be soldered to a thermal land for optimal heat dissipation. SI5338A-B01223-GM's typical core supply current is 45 mA at 100 MHz on all outputs, resulting in low self-heating - critical for thermally constrained networking and telecom modules.

SI5338A-B01223-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B01223-GM FAQ

1.How can I place an order for SI5338A-B01223-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B01223-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B01223-GM reliable?

The price and inventory of SI5338A-B01223-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B01223-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B01223-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B01223-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B01223-GM?

SI5338A-B01223-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B01223-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B01223-GM?

For technical support, including SI5338A-B01223-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B01223-GM requirements.

6.How does Aetrix verify that SI5338A-B01223-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B01223-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B01223-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B01223-GM?

All SI5338A-B01223-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B01223-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B01223-GM part is unused and in its original packaging.

Return procedure for SI5338A-B01223-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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