Skyworks Solutions Inc. SI5338A-B01224-GMR

Overview

SI5338A-B01224-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply. It replaces up to four crystal oscillators in high-speed serial interface timing applications including PCIe root complexes and FPGA-based compute platforms.

For engineers reviewing the SI5338A-B01224-GMR datasheet, SI5338A-B01224-GMR pinout, SI5338A-B01224-GMR application, or SI5338A-B01224-GMR equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent output voltage per driver (1.5–3.3 V), 0.16–710 MHz frequency range per output, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL signal formats.

Technical Context

The SI5338A-B01224-GMR implements a two-stage PLL architecture: a high-stability reference stage (Phase Detector + Loop Filter + VCO) feeding four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each output supports independent frequency, format, voltage, phase offset (<20 ps step resolution), spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), and glitchless frequency increment/decrement in 1 ppm steps. Loss-of-lock and loss-of-signal alarms are integrated, and configuration is performed via I²C/SMBus interface with OTP NVM storage.

Key Specifications

Pinout & Package

SI5338A-B01224-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with SI5338A-B01224-GMR, Si5332A-D06189-GM offers superior jitter and scalability but demands board redesign and higher cost, while ICS8430I-01LG provides lower unit cost only when full programmability, PCIe compliance, and flexible output formatting are unnecessary.

Availability

SI5338A-B01224-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10 GbE switching infrastructure, and FPGA-based broadcast video systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B01224-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for wireless, automotive, and infrastructure markets.

The Si5338 family is designed as a programmable, low-jitter clock generator platform for high-speed serial interfaces-specifically targeting PCIe, Ethernet, Fibre Channel, and broadcast video timing where multi-frequency, multi-format flexibility and sub-ps jitter are critical.

FAQ

What is the maximum output frequency supported by SI5338A-B01224-GMR in LVPECL mode?

The SI5338A-B01224-GMR supports up to 710 MHz in LVPECL mode when operating in integer synthesis mode. For frequencies above 350 MHz, only two unique outputs may simultaneously exceed that threshold (Fvco/4 and Fvco/6), as specified in the functional description section of the datasheet. This limitation ensures optimal VCO performance and jitter integrity across all active outputs.

Does SI5338A-B01224-GMR support PCIe Gen 4 Common Clock architecture?

Yes, SI5338A-B01224-GMR meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks' recommended settings-including PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This compliance is verified using the Skyworks PCIe Clock Jitter Tool and aligns with PCI-Express Base Specification 4.0 rev. 0.5.

Can SI5338A-B01224-GMR generate different output voltages on each of its four output banks?

Yes, SI5338A-B01224-GMR supports independent output supply voltages per bank: VDDO0, VDDO1, VDDO2, and VDDO3 can each be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O, 3.3 V legacy peripherals) without external level shifters, simplifying power domain partitioning.

Is an external crystal required for SI5338A-B01224-GMR operation?

No-SI5338A-B01224-GMR accepts multiple reference sources: an external 8–30 MHz crystal (connected to IN1/IN2), a single-ended CMOS clock (5–200 MHz on IN3/IN4), or differential inputs (5–710 MHz on IN1/IN2 or IN5/IN6). Crystal usage is optional; the device operates fully with any supported clock input, including recovered system clocks.

How is SI5338A-B01224-GMR programmed, and is configuration retained after power cycle?

SI5338A-B01224-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates custom configuration files. Configuration is stored in one-time-programmable (OTP) NVM, so the device boots with user-defined settings without host intervention. Factory-default or user-programmed configurations persist across power cycles without external memory.