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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B01316-GM

Name: SI5338A-B01316-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B01316-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B01316-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B01316-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B01316-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338A-B01316-GM datasheet, SI5338A-B01316-GM pinout, SI5338A-B01316-GM application, or SI5338A-B01316-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe Gen 4 jitter performance, and real-world substitution guidance for multi-output clock synthesis designs.

Technical Context

The SI5338A-B01316-GM implements a two-stage PLL architecture: a high-stability reference stage (Synthesis Stage 1) followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2), each driving one output pair. Each MultiSynth supports integer or fractional frequency synthesis from 0.16 MHz to 710 MHz with 1 ppb resolution.

It accepts six input sources - two differential (IN1/IN2, IN5/IN6), two single-ended CMOS (IN3/IN4), and two additional inputs (IN6 used as feedback in external loop mode) - and supports flexible output voltage per driver (1.5 V, 1.8 V, 2.5 V, or 3.3 V) with LVPECL, LVDS, HCSL, CML, SSTL, HSTL, and CMOS signal formats.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock RMS jitter ≤0.45 ps requirement when configured per spec.
Output Count & Type	Four differential output pairs (CLK0A/B through CLK3A/B); supports up to eight single-ended clocks or mixed format.
Frequency Range	0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz.
Input Flexibility	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential references.
Supply Voltages	Core: 1.8 V / 2.5 V / 3.3 V; Output buffers: independently configurable 1.4–3.63 V per VDDOx rail.
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad - optimized for high-density PCB layouts.
Temperature Range	–40 °C to +85 °C ambient; qualified for industrial and telecom line card deployment.

Pinout & Package

The SI5338A-B01316-GM is housed in a 24-lead QFN package (4 mm × 4 mm) with an exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVPECL/LVDS/CML references up to 710 MHz; require external 100 Ω termination.
IN3, IN4	Single-ended CMOS inputs	Support 5–200 MHz CMOS clocks; VIH ≥ 0.7×VDD, VIL ≤ 0.3×VDD; slew rate >1 V/ns recommended.
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each configurable for LVPECL, LVDS, HCSL, or CML with per-driver VDDO supply.
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output pair; enable mixed-voltage signaling on same device.
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz I²C control; supports ClockBuilder Pro programming and runtime reconfiguration.
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events.
VDD	Core supply	1.8 V / 2.5 V / 3.3 V ±10%; typical core current = 45 mA at 100 MHz on all outputs.
GND, RSVD_GND	Ground connections	Multiple dedicated GND pins and reserved ground pad ensure low-noise return paths and thermal dissipation.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously.
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 rev 0.5 common clock jitter requirements (≤0.45 ps RMS, 10 kHz–50 MHz).
Glitchless frequency tuning	Independent ±1 ppm step increment/decrement via pin control or I²C without output interruption.
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps step resolution for skew alignment.
Spread spectrum support	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz range.
External feedback mode	Enables zero-delay buffer operation using external clock source as feedback path.

Applications

PCIe Gen 4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks meeting PCIe Gen 4 common clock jitter specs. Use Value: Eliminates need for four discrete oscillators; reduces board area and BOM count while guaranteeing sub-0.45 ps RMS jitter compliance.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in enterprise switches. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting mixed-rate Ethernet interfaces from a single crystal reference. Use Value: Enables single-reference design across 1G/10G/25G lanes; avoids timing skew between ports and simplifies layout.
FPGA/ASIC Clock Tree	Broadcast Video Sync Generator
Use Scenario: Supplying multiple domain-specific clocks (e.g., 200 MHz logic, 300 MHz transceiver, 100 MHz DDR) to Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Programmable quad clock generator with independent voltage and format per output for heterogeneous FPGA clock domains. Use Value: Replaces discrete clock buffers and synthesizers; supports mixed LVDS/HCSL/CMOS signaling without level-shifting components.	Use Scenario: Deriving SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from a 25 MHz OCXO in broadcast camera systems. IC Role / Device Role / Timing Role: Low-phase-jitter frequency translator generating exact broadcast timing frequencies with zero ppm error. Use Value: Meets SMPTE jitter limits (<0.7 ps RMS) while enabling frame-accurate genlock across multiple video processing paths.

PCIe Gen 4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks meeting PCIe Gen 4 common clock jitter specs.

Use Value: Eliminates need for four discrete oscillators; reduces board area and BOM count while guaranteeing sub-0.45 ps RMS jitter compliance.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in enterprise switches.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting mixed-rate Ethernet interfaces from a single crystal reference.

Use Value: Enables single-reference design across 1G/10G/25G lanes; avoids timing skew between ports and simplifies layout.

FPGA/ASIC Clock Tree

Broadcast Video Sync Generator

Use Scenario: Supplying multiple domain-specific clocks (e.g., 200 MHz logic, 300 MHz transceiver, 100 MHz DDR) to Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Programmable quad clock generator with independent voltage and format per output for heterogeneous FPGA clock domains.

Use Value: Replaces discrete clock buffers and synthesizers; supports mixed LVDS/HCSL/CMOS signaling without level-shifting components.

Use Scenario: Deriving SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from a 25 MHz OCXO in broadcast camera systems.

IC Role / Device Role / Timing Role: Low-phase-jitter frequency translator generating exact broadcast timing frequencies with zero ppm error.

Use Value: Meets SMPTE jitter limits (<0.7 ps RMS) while enabling frame-accurate genlock across multiple video processing paths.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B01281-GM	Same silicon die and pinout; factory-programmed with different default configuration stored in OTP NVM.	Pre-configured for PCIe Gen 3 SRNS mode; lacks Gen 4 common clock optimization in default state.	Select if PCIe Gen 3 compliance suffices and factory-programmed startup behavior is preferred over field reprogrammability.
LMK04832ISQE/NOPB	Two-stage jitter cleaner + dual-loop PLL; higher power (125 mA), larger 48-QFN package; no integrated crystal oscillator circuitry.	Targeted at ultra-low-jitter cleaning (0.15 ps RMS) rather than multi-frequency synthesis; requires external VCXO.	Choose when additive jitter reduction below 0.2 ps RMS is required and system-level jitter budget is dominated by upstream sources.

Compared with SI5338A-B01316-GM, Si5338A-B01281-GM offers identical hardware but fixed factory firmware, while LMK04832ISQE/NOPB trades programmability for superior jitter cleaning - making SI5338A-B01316-GM optimal for flexible, space-constrained any-frequency generation where PCIe Gen 4 compliance is mandatory.

Availability

SI5338A-B01316-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10/25 GbE switching infrastructure, broadcast video equipment, and FPGA-based industrial controllers requiring stable component supply and long-term lifecycle support.

Supply support for SI5338A-B01316-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications, automotive, and industrial markets.

The Si5338 product line was designed specifically for high-performance, multi-output clock synthesis in datacenter, networking, and broadcast applications where flexibility, low jitter, and compact footprint are critical.

FAQ

What is the default factory configuration of the SI5338A-B01316-GM?

The SI5338A-B01316-GM ships with non-volatile memory (OTP) pre-programmed for PCIe Gen 4 Common Clock operation using a 25 MHz crystal reference, with all four outputs enabled as LVDS at 100 MHz and default spread-spectrum disabled. This configuration is verified in Skyworks' official device configuration file B01316.

Does the SI5338A-B01316-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338A-B01316-GM supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical) when configured with PLL bandwidth 2–5 MHz and CDR = 10 MHz. This capability is documented in Table 12 of the Rev. 1.6 datasheet and validated using the Skyworks PCIe Clock Jitter Tool.

Can the SI5338A-B01316-GM generate three different frequencies above 350 MHz simultaneously?

No. The SI5338A-B01316-GM can output only two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency division constraints. This limitation is explicitly stated in Note 6 of Table 6 in the datasheet.

What is the maximum allowable input slew rate for differential clock signals on IN1/IN2?

The SI5338A-B01316-GM requires a minimum differential input slew rate of >0.3 V/ns on IN1/IN2 for optimal jitter performance. Exceeding 1.0 V/ns is acceptable and improves noise immunity, but rates below 0.3 V/ns degrade RMS jitter beyond the 0.7 ps typical specification.

Is the SI5338A-B01316-GM pin-compatible with other Si5338 variants like SI5338A-B01281-GM?

Yes, the SI5338A-B01316-GM is fully pin-compatible with all Si5338A-x-x-GM variants in the 24-QFN package, including SI5338A-B01281-GM. All share identical pin assignments, electrical characteristics, and thermal profiles - only the factory-programmed OTP configuration differs.

SI5338A-B01316-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B01316-GM FAQ

1.How can I place an order for SI5338A-B01316-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B01316-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B01316-GM reliable?

The price and inventory of SI5338A-B01316-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B01316-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B01316-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B01316-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B01316-GM?

SI5338A-B01316-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B01316-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B01316-GM?

For technical support, including SI5338A-B01316-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B01316-GM requirements.

6.How does Aetrix verify that SI5338A-B01316-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B01316-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B01316-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B01316-GM?

All SI5338A-B01316-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B01316-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B01316-GM part is unused and in its original packaging.

Return procedure for SI5338A-B01316-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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