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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B01316-GMR

Name: SI5338A-B01316-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B01316-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B01316-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B01316-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B01316-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B01316-GMR datasheet, SI5338A-B01316-GMR pinout, SI5338A-B01316-GMR application, or SI5338A-B01316-GMR equivalent, key selection criteria include multi-format output support (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis down to 0.16 MHz, spread-spectrum capability (0.5–5.0% at 33–63 kHz), and glitchless frequency adjustment in 1 ppm steps.

Technical Context

The SI5338A-B01316-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Its input flexibility supports external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential clocks (5–710 MHz).

Each output driver supports independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL), voltage (1.5/1.8/2.5/3.3 V), phase offset (±45 ns in <20 ps steps), and spread-spectrum modulation-enabling precise timing alignment and EMI reduction across heterogeneous system domains without external components.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements.
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing.
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V - simplifies mixed-voltage board design.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient for dense FPGA/ASIC timing layouts.
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom line card environments.
Power Consumption	45 mA typical core current at 100 MHz on all outputs and 25 MHz refclk - low thermal impact in fanless systems.

Pinout & Package

SI5338A-B01316-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair	Accepts 5–710 MHz AC-coupled differential reference; internal 100 Ω termination enabled.
IN3, IN4	Single-ended CMOS inputs	Support 5–200 MHz DC-coupled clocks; VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent output channels; each configurable as LVPECL/LVDS/HCSL/CML with per-channel VDDO.
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank - enables mixed-signal interface voltage matching.
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz I²C control; supports ClockBuilder Pro programming and runtime reconfiguration.
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events.
VDD	Core supply	Single 1.8/2.5/3.3 V supply powers PLL, synthesizers, and logic; PSRR optimized for noisy environments.
GND, RSVD_GND	Ground terminals	Multiple dedicated GND pins and reserved ground pad ensure low-impedance return paths for high-frequency outputs.

Key Features

Feature	Design Value
Any-frequency synthesis	Four independent outputs with 0 ppm precision via MultiSynth™ fractional-N synthesis - eliminates need for multiple crystals or discrete PLLs.
PCIe Gen 1–4 compliance	Meets Common Clock and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS); validated using Intel Clock Jitter Tool and Skyworks PCIe Jitter Tool.
Glitchless frequency tuning	Independent ±1 ppm step frequency increment/decrement via pin or I²C - enables dynamic clock scaling without output interruption.
Programmable phase offset	Per-output phase adjustment from –45 ns to +45 ns in <20 ps steps - supports precise skew compensation in SerDes lanes.
Configurable spread spectrum	On any output: 0.5–5.0% spread, 33–63 kHz modulation rate - reduces EMI peak emissions without affecting timing integrity.
Flexible input architecture	Five input options (crystal, CMOS, SSTL, HSTL, differential) with automatic detection - simplifies migration across reference sources.

Applications

Ethernet Switch Timing	PCIe Gen 4 Root Complex
Use Scenario: 10 GbE switch fabric requiring synchronized 156.25 MHz and 312.5 MHz clocks for MAC/PHY and SerDes interfaces. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, phase-aligned outputs - one for reference, three for data lanes - with independent voltage and format control. Use Value: Replaces four discrete oscillators; achieves <0.7 ps RMS jitter on all outputs, meeting IEEE 802.3bj and PCIe Gen 4 common clock specifications.	Use Scenario: Server motherboard with PCIe Gen 4 x16 slot, CPU, and NVMe controller needing compliant 100 MHz reference clocks with tight skew control. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering four 100 MHz HCSL outputs with SRNS validation and <0.32 ps RMS jitter (Gen 3) or <0.45 ps RMS (Gen 4). Use Value: Eliminates external jitter cleaners; supports zero-delay mode via external feedback; enables board-level timing margin optimization through programmable phase offsets.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: 4K/8K video encoder requiring genlock-capable 74.25 MHz, 148.5 MHz, and 297 MHz clocks aligned to external tri-level sync signal. IC Role / Device Role / Timing Role: Frequency translator and jitter cleaner accepting tri-level sync as differential input (IN1/IN2), generating multiple harmonically related outputs with sub-20 ps phase step resolution. Use Value: Achieves <10 ps pk-pk period jitter and <9 ps pk-pk cycle-cycle jitter - satisfies SMPTE ST 2059-2 PTP timing accuracy for broadcast infrastructure.	Use Scenario: High-speed digital pattern generator using FPGA with multiple clock domains (125 MHz AXI, 250 MHz DDR, 500 MHz sampling) requiring deterministic phase relationships. IC Role / Device Role / Timing Role: Programmable multi-frequency source with independent phase offset per output - enabling precise setup/hold timing control across asynchronous interfaces. Use Value: Enables real-time frequency and phase tuning via I²C during test execution; supports spread-spectrum on non-critical clocks to reduce measurement noise floor.

Ethernet Switch Timing

PCIe Gen 4 Root Complex

Use Scenario: 10 GbE switch fabric requiring synchronized 156.25 MHz and 312.5 MHz clocks for MAC/PHY and SerDes interfaces.

IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, phase-aligned outputs - one for reference, three for data lanes - with independent voltage and format control.

Use Value: Replaces four discrete oscillators; achieves <0.7 ps RMS jitter on all outputs, meeting IEEE 802.3bj and PCIe Gen 4 common clock specifications.

Use Scenario: Server motherboard with PCIe Gen 4 x16 slot, CPU, and NVMe controller needing compliant 100 MHz reference clocks with tight skew control.

IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering four 100 MHz HCSL outputs with SRNS validation and <0.32 ps RMS jitter (Gen 3) or <0.45 ps RMS (Gen 4).

Use Value: Eliminates external jitter cleaners; supports zero-delay mode via external feedback; enables board-level timing margin optimization through programmable phase offsets.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: 4K/8K video encoder requiring genlock-capable 74.25 MHz, 148.5 MHz, and 297 MHz clocks aligned to external tri-level sync signal.

IC Role / Device Role / Timing Role: Frequency translator and jitter cleaner accepting tri-level sync as differential input (IN1/IN2), generating multiple harmonically related outputs with sub-20 ps phase step resolution.

Use Value: Achieves <10 ps pk-pk period jitter and <9 ps pk-pk cycle-cycle jitter - satisfies SMPTE ST 2059-2 PTP timing accuracy for broadcast infrastructure.

Use Scenario: High-speed digital pattern generator using FPGA with multiple clock domains (125 MHz AXI, 250 MHz DDR, 500 MHz sampling) requiring deterministic phase relationships.

IC Role / Device Role / Timing Role: Programmable multi-frequency source with independent phase offset per output - enabling precise setup/hold timing control across asynchronous interfaces.

Use Value: Enables real-time frequency and phase tuning via I²C during test execution; supports spread-spectrum on non-critical clocks to reduce measurement noise floor.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B01281-GM	Same Si5338A die, different factory-programmed configuration; lacks pre-loaded PCIe Gen 4 SRNS profile and specific spread-spectrum settings of SI5338A-B01316-GMR.	Requires full ClockBuilder Pro reconfiguration for PCIe Gen 4 compliance; not pre-validated for SRNS mode.	Select SI5338A-B01316-GMR when PCIe Gen 4 SRNS timing compliance must be guaranteed out-of-box without engineering effort.
LMK04832RHAT	Two PLLs (not four independent MultiSynths); higher power (120 mA typical); larger 48-QFN package; supports JESD204B but no native PCIe SRNS validation.	Targeted at JESD204B converter timing; less optimal for PCIe-centric designs due to higher jitter (0.95 ps RMS) and no SRNS-certified configuration.	Choose LMK04832RHAT only if dual-loop cascaded PLL architecture or JESD204B-specific features are required over PCIe Gen 4 timing assurance.

Compared with SI5338A-B01316-GMR, the Si5338A-B01281-GM requires post-manufacturing configuration to achieve identical PCIe Gen 4 performance, while the LMK04832RHAT trades lower integration density and higher jitter for JESD204B support - making SI5338A-B01316-GMR the optimal choice for PCIe- and Ethernet-dominant platforms demanding pre-validated, low-jitter quad-clock generation.

Availability

SI5338A-B01316-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switch fabrics, and broadcast video synchronizers requiring stable component supply, long-term lifecycle support, and guaranteed pre-programmed timing compliance.

Supply support for SI5338A-B01316-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for wireless infrastructure, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, and broadcast video - designed to replace multiple discrete oscillators while maintaining sub-picosecond jitter performance.

FAQ

What is the default factory configuration of the SI5338A-B01316-GMR?

The SI5338A-B01316-GMR ships with a pre-programmed configuration optimized for PCIe Gen 4 Common Clock compliance, including validated 100 MHz HCSL outputs, SRNS-mode PLL bandwidth (2–4 MHz), and default spread-spectrum disabled. This configuration is stored in one-time-programmable (OTP) memory and can be modified via I²C using ClockBuilder Pro software. The SI5338A-B01316-GMR does not require initial programming to operate in PCIe Gen 4 systems.

Does the SI5338A-B01316-GMR support spread-spectrum clocking on all four outputs simultaneously?

Yes, the SI5338A-B01316-GMR supports independent spread-spectrum modulation on any or all four outputs. Each output can be configured with unique spread percentage (0.5–5.0%), modulation rate (33–63 kHz), and center-spread or down-spread mode. This capability is implemented in hardware per output stage and does not require shared resources - enabling simultaneous EMI reduction across multiple high-speed interfaces driven by the SI5338A-B01316-GMR.

Can the SI5338A-B01316-GMR generate frequencies above 350 MHz on more than two outputs?

No. The SI5338A-B01316-GMR supports frequencies above 350 MHz on only two unique outputs simultaneously - specifically Fvco/4 and Fvco/6 - due to internal VCO frequency constraints. For example, it can deliver 473.33 MHz on CLK0A/CLK0B and 367 MHz on CLK1A/CLK1B, but cannot sustain three or more outputs >350 MHz. Outputs above 350 MHz must use LVPECL, LVDS, or CML formats, and the SI5338A-B01316-GMR's datasheet explicitly limits concurrent high-frequency operation to two channels.

How does the SI5338A-B01316-GMR handle loss-of-signal (LOS) detection on its input pins?

The SI5338A-B01316-GMR provides dedicated loss-of-signal detection on all six input pins (IN1–IN6) with programmable thresholds. Detection time is 2.6–5 µs for assertion and 0.01–1 µs for release, and status is reported via the INTR pin and internal registers. When LOS is detected, the device holds last valid output state or enters a user-defined fail-safe mode - critical for maintaining system stability in redundant clock architectures using the SI5338A-B01316-GMR.

Is the SI5338A-B01316-GMR pin-compatible with other Si5338 variants like the SI5338A-B01281-GM?

Yes, the SI5338A-B01316-GMR is fully pin-compatible with all Si5338A variants in the 24-QFN package, including the SI5338A-B01281-GM. All share identical pin assignments, electrical characteristics, thermal profile, and PCB land pattern. The functional differences between SI5338A-B01316-GMR and other Si5338A variants reside solely in factory-programmed OTP configuration - not in pinout, package, or hardware functionality.

SI5338A-B01316-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B01316-GMR FAQ

1.How can I place an order for SI5338A-B01316-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B01316-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B01316-GMR reliable?

The price and inventory of SI5338A-B01316-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B01316-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B01316-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B01316-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B01316-GMR?

SI5338A-B01316-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B01316-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B01316-GMR?

For technical support, including SI5338A-B01316-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B01316-GMR requirements.

6.How does Aetrix verify that SI5338A-B01316-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B01316-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B01316-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B01316-GMR?

All SI5338A-B01316-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B01316-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B01316-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B01316-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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