Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B01343-GMR

Name: SI5338A-B01343-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B01343-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338A-B01343-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B01343-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,704

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338A-B01343-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ), PCIe Gen 1–4 compliance, and support for LVPECL/LVDS/HCSL/CMOS outputs up to 710 MHz. It replaces multiple crystal oscillators in high-speed networking and FPGA timing applications.

For engineers reviewing the SI5338A-B01343-GMR datasheet, SI5338A-B01343-GMR pinout, SI5338A-B01343-GMR application, or SI5338A-B01343-GMR equivalent, key selection criteria include differential output jitter performance (0.7 ps RMS), PCIe Gen 4 SRNS compliance, independent per-output voltage control (1.5–3.3 V), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338A-B01343-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. This enables true zero-ppm frequency accuracy across all four outputs without shared dividers or frequency coupling.

It supports flexible input references-including 8–30 MHz crystals, 5–200 MHz CMOS, and 5–710 MHz differential inputs-and provides independent phase adjustment (<20 ps steps), glitchless frequency increment/decrement (1 ppm steps), and programmable spread spectrum on any output (0.5–5.0% spread, 33–63 kHz modulation).

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical over 12 kHz–20 MHz - meets PCIe Gen 4 common clock and SRNS requirements
Output Count & Type	4 differential outputs (CLK0A/B through CLK3A/B) - supports LVPECL, LVDS, HCSL, CML, SSTL, HSTL, CMOS
Frequency Range	0.16–710 MHz per output - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, and Fibre Channel 1.0625 GHz (via /2)
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - enables mixed-voltage system interfacing without level shifters
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - surface-mount compatible with standard reflow profiles and IPC-7351B land pattern
Operating Temp	–40 °C to +85 °C - qualified for industrial and telecom line card environments
I²C Interface	SMBus-compatible, 100/400 kHz - enables in-system configuration and dynamic frequency tuning during operation

Pinout & Package

SI5338A-B01343-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad (GND). Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential Input Pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-Ended Inputs	Support 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential Output Pairs	Four independent output drivers; each configurable for format, voltage, and enable
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank - eliminates level-shifting ICs
SCL, SDA, INTR	I²C Control Interface	Standard bidirectional I²C bus with interrupt flag for loss-of-lock/loss-of-signal detection
VDD, GND, RSVD_GND	Core Power & Ground	1.8/2.5/3.3 V core supply; dedicated ground pins reduce noise coupling between analog/digital sections

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enabling simultaneous, unrelated frequencies (e.g., 100 MHz PCIe + 125 MHz Ethernet + 156.25 MHz SerDes + 200 MHz processor clock)
PCIe Gen 4 Compliance	0.15–0.45 ps RMS jitter in Common Clock mode and SRNS mode - verified per PCI-SIG Base Spec 4.0 rev 0.5
Per-Output Voltage Control	Each of four output banks powered by separate VDDOx rail (1.5/1.8/2.5/3.3 V) - simplifies multi-voltage SoC/FPGA interface design
Glitchless Frequency Tuning	Hardware-supported ±1 ppm frequency step via PINC/FDEC pins - enables real-time clock margining without software intervention
Programmable Phase Offset	±45 ns initial phase offset per output with <20 ps resolution - critical for skew-sensitive parallel interfaces (e.g., DDR memory, JESD204B)
Spread Spectrum Support	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI peak emissions in dense PCB layouts

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE PHY Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to PCIe Gen 4 switch ASICs and attached endpoints in data center top-of-rack switches. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with SRNS support and deterministic inter-output skew ≤100 ps. Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 jitter mask (0.32 ps RMS) and enabling board-level power savings (45 mA core current).	Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE PHYs and MACs in enterprise routers and optical transport equipment. IC Role / Device Role / Timing Role: Configurable clock source supporting both LVDS and HCSL outputs at 156.25 MHz and 312.5 MHz simultaneously, with independent voltage control per bank. Use Value: Enables single-device timing for multi-rate Ethernet PHYs, reducing BOM count and layout complexity versus discrete clock trees.
FPGA High-Speed Transceiver Reference	Broadcast Video Sync Generator
Use Scenario: Supplying precise, low-jitter reference clocks to Xilinx Versal or Intel Agilex FPGA transceivers operating at 10–28 Gbps. IC Role / Device Role / Timing Role: Programmable clock generator synthesizing exact SerDes reference frequencies (e.g., 148.5 MHz, 297 MHz, 594 MHz) with sub-1 ps RMS jitter and programmable phase alignment. Use Value: Ensures clean eye diagrams and low bit error rates in high-speed serial links; I²C reprogramming allows field-upgradable clock plans.	Use Scenario: Generating SMPTE ST 2059-2 compliant PTP grandmaster clocks and genlock signals for broadcast video encoders, IP media gateways, and SDI-to-IP converters. IC Role / Device Role / Timing Role: Precision timing IC providing 27 MHz, 74.25 MHz, and 148.5 MHz outputs with <20 ps phase step resolution for frame-accurate synchronization. Use Value: Meets SMPTE ST 2059-2 wander and jitter requirements (≤100 ps RMS) while supporting dual-reference redundancy via IN1/IN2 inputs.

PCIe Gen 4 Switch Timing

Ethernet 10GbE PHY Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to PCIe Gen 4 switch ASICs and attached endpoints in data center top-of-rack switches.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with SRNS support and deterministic inter-output skew ≤100 ps.

Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 jitter mask (0.32 ps RMS) and enabling board-level power savings (45 mA core current).

Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE PHYs and MACs in enterprise routers and optical transport equipment.

IC Role / Device Role / Timing Role: Configurable clock source supporting both LVDS and HCSL outputs at 156.25 MHz and 312.5 MHz simultaneously, with independent voltage control per bank.

Use Value: Enables single-device timing for multi-rate Ethernet PHYs, reducing BOM count and layout complexity versus discrete clock trees.

FPGA High-Speed Transceiver Reference

Broadcast Video Sync Generator

Use Scenario: Supplying precise, low-jitter reference clocks to Xilinx Versal or Intel Agilex FPGA transceivers operating at 10–28 Gbps.

IC Role / Device Role / Timing Role: Programmable clock generator synthesizing exact SerDes reference frequencies (e.g., 148.5 MHz, 297 MHz, 594 MHz) with sub-1 ps RMS jitter and programmable phase alignment.

Use Value: Ensures clean eye diagrams and low bit error rates in high-speed serial links; I²C reprogramming allows field-upgradable clock plans.

Use Scenario: Generating SMPTE ST 2059-2 compliant PTP grandmaster clocks and genlock signals for broadcast video encoders, IP media gateways, and SDI-to-IP converters.

IC Role / Device Role / Timing Role: Precision timing IC providing 27 MHz, 74.25 MHz, and 148.5 MHz outputs with <20 ps phase step resolution for frame-accurate synchronization.

Use Value: Meets SMPTE ST 2059-2 wander and jitter requirements (≤100 ps RMS) while supporting dual-reference redundancy via IN1/IN2 inputs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D07189-GM	Higher integration: 8 outputs, integrated crystal, lower jitter (0.35 ps RMS), but larger 32-QFN package and higher cost	Preferred for new designs requiring >4 outputs or crystal-less operation; not drop-in due to pin count and footprint change	Select when needing ≥8 outputs or eliminating external crystal; avoid if constrained to 24-QFN footprint or cost-sensitive.
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock buffer; no synthesis capability; jitter = 0.9 ps RMS	Only suitable for static clock fanout-not frequency translation or multi-format generation	Choose only for simple clock distribution where frequencies are fixed and I²C programming is unnecessary.

Compared with SI5338A-B01343-GMR, Si5332A-D07189-GM offers superior jitter and integration but requires PCB redesign, while ICS8430I-01T lacks programmability and synthesis-making SI5338A-B01343-GMR the optimal balance of flexibility, performance, and 24-QFN compatibility for mid-complexity timing systems.

Availability

SI5338A-B01343-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE PHY clocking, and FPGA transceiver reference applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B01343-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.

The Si5338 product line delivers highly configurable, low-jitter clock generators for high-speed digital systems-including data centers, telecom infrastructure, and broadcast video-where deterministic timing and multi-format flexibility are critical.

FAQ

What is the maximum output frequency supported by the SI5338A-B01343-GMR?

The SI5338A-B01343-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints. All outputs maintain 0.7 ps RMS jitter at 100 MHz and meet PCIe Gen 4 specifications.

Does the SI5338A-B01343-GMR support spread spectrum clocking (SSC)?

Yes, the SI5338A-B01343-GMR supports fully programmable spread spectrum on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, and selectable up/down-center spread. SSC is configured independently per output via I²C registers and does not affect other outputs' stability or jitter performance.

Can the SI5338A-B01343-GMR operate without an external crystal?

Yes - the SI5338A-B01343-GMR accepts multiple reference inputs: external 8–30 MHz crystal (on IN1/IN2), 5–200 MHz CMOS clock (on IN3/IN4), or 5–710 MHz differential clock (on IN1/IN2 or IN5/IN6). Crystal operation requires no additional components beyond load capacitors; no internal oscillator is present.

How is output voltage configured for each clock bank on the SI5338A-B01343-GMR?

Each of the four output banks (CLK0, CLK1, CLK2, CLK3) has its own dedicated VDDOx supply pin (VDDO0–VDDO3), allowing independent selection of 1.5 V, 1.8 V, 2.5 V, or 3.3 V per bank. This eliminates external level shifters when driving mixed-voltage devices like 1.8 V FPGAs and 3.3 V legacy peripherals from a single SI5338A-B01343-GMR.

Is the SI5338A-B01343-GMR pin-compatible with other Si5338 variants?

Yes - all Si5338 variants (including SI5338A-B01343-GMR) share identical 24-QFN pinout, package dimensions, and thermal pad layout. Firmware and register maps are also consistent across the family; only factory-programmed NVM content (e.g., default frequency plan) differs between part numbers.

SI5338A-B01343-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B01343-GMR FAQ

1.How can I place an order for SI5338A-B01343-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B01343-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B01343-GMR reliable?

The price and inventory of SI5338A-B01343-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B01343-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B01343-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B01343-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B01343-GMR?

SI5338A-B01343-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B01343-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B01343-GMR?

For technical support, including SI5338A-B01343-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B01343-GMR requirements.

6.How does Aetrix verify that SI5338A-B01343-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B01343-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B01343-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B01343-GMR?

All SI5338A-B01343-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B01343-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B01343-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B01343-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…