Skyworks Solutions Inc. SI5338A-B01603-GM

Overview

SI5338A-B01603-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ PLL synthesis with 0 ppm frequency accuracy on all four outputs. It delivers low phase jitter of 0.7 ps RMS (typ), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz, and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 and Ethernet timing applications.

For engineers reviewing the SI5338A-B01603-GM datasheet, SI5338A-B01603-GM pinout, SI5338A-B01603-GM application, or SI5338A-B01603-GM equivalent, this page provides verified technical context, pin-level design meaning, PCIe Gen 4 SRNS-compliant jitter performance, and validated alternative options for multi-frequency clocking in FPGA, processor, and telecom line card designs.

Technical Context

The SI5338A-B01603-GM integrates a two-stage synthesis architecture: a high-stability PLL stage (1.6 MHz loop bandwidth) followed by four independent MultiSynth™ fractional-N dividers per output. Each output driver supports programmable voltage (1.5/1.8/2.5/3.3 V), format selection, and sub-20 ps phase step resolution.

It accepts flexible references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and enables glitchless frequency increment/decrement in 1 ppm steps via dedicated control pins or I²C. Loss-of-lock and loss-of-signal alarms are integrated.

Key Specifications

Pinout & Package

The SI5338A-B01603-GM uses a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and include six input pins (IN1–IN6), eight clock output terminals (CLK0A/B through CLK3A/B), four VDDOx supplies, dual VDD core rails, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5338A-B01604-GM, the SI5338A-B01603-GM offers identical hardware but distinct factory NVM settings - ideal for new designs requiring custom clock maps. Versus LMK04832RHAR, it trades JESD204B features for lower power, smaller footprint, and guaranteed zero-ppm synthesis across all four outputs.

Availability

SI5338A-B01603-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE PHY clocking, FPGA I/O bank distribution, and broadcast video sync generation requiring stable component supply and long-term lifecycle support.

Supply support for SI5338A-B01603-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace multiple discrete oscillators with a single programmable IC.

FAQ

What is the primary function of the SI5338A-B01603-GM in a timing architecture?

The SI5338A-B01603-GM functions as a quad-output, I²C-programmable clock generator that synthesizes any frequency from a single reference using MultiSynth™ technology. It replaces up to four discrete oscillators while delivering 0 ppm frequency accuracy, sub-1 ps RMS jitter, and independent output configuration - making it ideal for PCIe Gen 4, 10GbE, and FPGA clocking where precision and flexibility are critical. The SI5338A-B01603-GM integrates both PLL and fractional-N synthesis stages to achieve this performance.

Does the SI5338A-B01603-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, the SI5338A-B01603-GM is explicitly specified for PCIe Gen 4 SRNS operation with 0.11–0.32 ps RMS jitter (typ) under defined test conditions: PLL bandwidth of 2–4 MHz, CDR = 10 MHz, and HCSL 100 MHz outputs. This performance is validated per PCI-Express Base Specification 4.0 rev 0.5 and confirmed using the Skyworks PCIe Clock Jitter Tool. The SI5338A-B01603-GM achieves this via its low-noise VCO, optimized loop filter, and differential output architecture.

Can the SI5338A-B01603-GM generate four different output frequencies simultaneously?

Yes, the SI5338A-B01603-GM supports four fully independent output frequencies simultaneously - each synthesized by a dedicated MultiSynth™ divider with no shared dividers or frequency constraints. Outputs can range from 0.16 MHz to 710 MHz (with two outputs above 350 MHz limited to Fvco/4 and Fvco/6), and each may use different signal formats (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL) and supply voltages (1.5/1.8/2.5/3.3 V). This capability is inherent to the SI5338A-B01603-GM's architecture and requires no external components.

What reference inputs does the SI5338A-B01603-GM accept?

The SI5338A-B01603-GM accepts five reference input types: (1) 8–30 MHz fundamental-mode crystal on IN1/IN2; (2) 5–200 MHz CMOS on IN3/IN4; (3) 5–350 MHz SSTL or HSTL on IN3/IN4; (4) 5–710 MHz differential (LVDS/LVPECL/CML) on IN1/IN2 or IN5/IN6; and (5) external feedback in zero-delay mode. All inputs are validated across –40 °C to +85 °C, and the SI5338A-B01603-GM includes loss-of-signal detection with 2.6–5 µs response time.

How is the SI5338A-B01603-GM programmed and configured?

The SI5338A-B01603-GM is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins), supporting standard 400 kHz fast-mode operation. Configuration is typically performed using Skyworks' ClockBuilder Pro software, which generates register maps and .hex files for factory programming or in-system updates. The SI5338A-B01603-GM also supports pin-controlled frequency increment/decrement and phase adjustment without I²C intervention, and stores configuration in one-time-programmable (OTP) NVM for immediate operation after power-up.