Skyworks Solutions Inc. SI5338A-B01603-GMR

Overview

SI5338A-B01603-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338A-B01603-GMR datasheet, SI5338A-B01603-GMR pinout, SI5338A-B01603-GMR application, or SI5338A-B01603-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum control (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338A-B01603-GMR implements a two-stage PLL architecture: a high-stability reference stage (input frequency range 5–710 MHz) followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its synthesis resolution is 1 ppb, enabling true zero-ppm frequency accuracy across all outputs.

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage rails (VDDO0–VDDO3), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). The device includes loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation).

Key Specifications

Pinout & Package

SI5338A-B01603-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, page 33.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with SI5338A-B01603-GMR, the B01604 variant offers identical silicon performance but different factory defaults, while the LMK04832 provides greater output count and JESD204B features at the cost of size, power, and pin compatibility-making SI5338A-B01603-GMR optimal for space-constrained PCIe/FPGA clocking where four precisely tunable outputs suffice.

Availability

SI5338A-B01603-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, FPGA clock distribution, and 10 GbE switch applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B01603-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, and broadcast video, emphasizing flexibility, integration, and signal integrity in compact packages.

FAQ

What is the primary function of the SI5338A-B01603-GMR?

The SI5338A-B01603-GMR is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks (0.16–710 MHz) from a single input reference. It replaces multiple discrete oscillators in systems requiring precise timing for PCIe, Ethernet, FPGA, and processor subsystems. Its MultiSynth™ architecture ensures 0 ppm frequency accuracy on all outputs, and it operates from 1.8/2.5/3.3 V supply in a 4 × 4 mm QFN package.

Does the SI5338A-B01603-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338A-B01603-GMR meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks AN562 guidelines. It achieves this using its high-performance MultiSynth™ PLL with 2–5 MHz loop bandwidth and supports both Common Clock and Gen 3 SRNS modes. Validation is confirmed using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

How many output formats does the SI5338A-B01603-GMR support per channel?

The SI5338A-B01603-GMR supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, and HSTL output formats across its four differential output pairs (CLK0A/B through CLK3A/B). Each output driver is independently configurable for format and supply voltage (VDDO0–VDDO3 = 1.4–3.63 V), enabling mixed-format clock distribution-for example, LVDS for SerDes and CMOS for microcontrollers on the same device.

Can the SI5338A-B01603-GMR operate in clock buffer (PLL bypass) mode?

Yes, the SI5338A-B01603-GMR supports clock buffer mode, where the input clock passes directly to outputs with minimal additive jitter (0.165 ps RMS, 12 kHz–20 MHz). This mode disables the PLL and uses internal dividers for frequency translation only. It requires configuration via I²C register writes and supports input frequencies from 1 MHz (with LOS disabled) to 710 MHz, making it suitable for low-latency, jitter-sensitive fanout applications.

What development tools are available for configuring the SI5338A-B01603-GMR?

Skyworks provides ClockBuilder Pro software for intuitive GUI-based configuration of the SI5338A-B01603-GMR, including frequency planning, jitter optimization, and register file generation. The tool exports I²C initialization scripts and supports hardware evaluation via USB-to-I²C adapters. Additionally, the free Skyworks PCIe Clock Jitter Tool validates timing compliance against PCIe specifications using oscilloscope data.