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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B02426-GMR

Name: SI5338A-B02426-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B02426-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B02426-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B02426-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B02426-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B02426-GMR datasheet, SI5338A-B02426-GMR pinout, SI5338A-B02426-GMR application, or SI5338A-B02426-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), 1 ppm frequency increment/decrement resolution, <20 ps phase step accuracy, and 24-pin 4×4 mm QFN package compatibility.

Technical Context

The SI5338A-B02426-GMR implements a two-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers in Stage 2. Each output driver operates with its own R-divider, M-divider, and P-divider configuration, enabling true zero-ppm frequency accuracy on all four outputs simultaneously.

It supports flexible reference inputs (8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential), independent output format selection per channel, and programmable spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation rate) on any output. Loss-of-lock and loss-of-signal alarms are provided via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS)
Output Count & Type	4 differential clock outputs (CLK0A/B through CLK3A/B); supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Input Reference Support	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temp	–40 °C to +85 °C; qualified for industrial and telecom line card environments

Pinout & Package

SI5338A-B02426-GMR is housed in a 24-lead, 4 × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin 1 is top-left corner (IN1), pin numbering proceeds counterclockwise. The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output channels; each pair (e.g., CLK0A/CLK0B) delivers complementary signals
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enable mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; PSRR optimized for low-noise clock generation
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events
RSVD_GND	Reserved ground	Internal no-connect; must be connected to PCB ground for thermal and EMI integrity

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable simultaneous zero-ppm precision at arbitrary frequencies without external crystals
PCIe Gen 4 compliance	Validated 0.15–0.45 ps RMS jitter in common clock mode per PCI Express Base Spec 4.0 rev. 0.5
Per-output voltage control	Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), eliminating level-shifter ICs in multi-voltage FPGA/ASIC systems
Glitchless frequency tuning	1 ppm incremental/decremental frequency adjustment via PINC/FDEC pins with sub-ns update latency
Programmable phase offset	±45 ns initial phase shift per output with <20 ps step resolution for skew compensation in parallel data paths
Spread spectrum clocking	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI peak emissions

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a 1U server chassis. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks compliant with PCIe Gen 4 SRNS requirements. Use Value: Eliminates four discrete oscillators while maintaining <0.32 ps RMS jitter per output-meeting Intel's PCIe Gen 4 CDR tolerance.	Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10 GbE PHYs and packet processors in a carrier-grade Ethernet switch. IC Role / Device Role / Timing Role: Frequency translator converting a single 25 MHz crystal reference into multiple Ethernet-compliant rates with deterministic phase alignment. Use Value: Achieves <0.79 ps RMS random jitter (1.875–20 MHz) on 125 MHz outputs-exceeding IEEE 802.3bj jitter limits for 10GBASE-KR.
Broadcast Video Sync	FPGA-Based Video Processing
Use Scenario: Distributing SMPTE ST 2082 (27 Gbps) reference clocks across video processing modules in a broadcast camera head. IC Role / Device Role / Timing Role: Low-phase-noise clock generator synthesizing 270 MHz, 1.5 GHz, and 2.7 GHz outputs from a 27 MHz crystal reference. Use Value: Delivers <10 ps pk-pk period jitter at 2.7 GHz-enabling clean sampling of UHD-SDI signals without timing-induced pixel errors.	Use Scenario: Supplying 300 MHz LVDS and 100 MHz HCSL clocks to Xilinx Versal ACAP fabric and memory interfaces in real-time video analytics hardware. IC Role / Device Role / Timing Role: Configurable buffer and level translator generating mixed-format clocks from a single 100 MHz differential input. Use Value: Enables direct connection to both FPGA I/O banks and DDR4 memory controllers without external voltage translators or fanout buffers.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a 1U server chassis.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks compliant with PCIe Gen 4 SRNS requirements.

Use Value: Eliminates four discrete oscillators while maintaining <0.32 ps RMS jitter per output-meeting Intel's PCIe Gen 4 CDR tolerance.

Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10 GbE PHYs and packet processors in a carrier-grade Ethernet switch.

IC Role / Device Role / Timing Role: Frequency translator converting a single 25 MHz crystal reference into multiple Ethernet-compliant rates with deterministic phase alignment.

Use Value: Achieves <0.79 ps RMS random jitter (1.875–20 MHz) on 125 MHz outputs-exceeding IEEE 802.3bj jitter limits for 10GBASE-KR.

Broadcast Video Sync

FPGA-Based Video Processing

Use Scenario: Distributing SMPTE ST 2082 (27 Gbps) reference clocks across video processing modules in a broadcast camera head.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator synthesizing 270 MHz, 1.5 GHz, and 2.7 GHz outputs from a 27 MHz crystal reference.

Use Value: Delivers <10 ps pk-pk period jitter at 2.7 GHz-enabling clean sampling of UHD-SDI signals without timing-induced pixel errors.

Use Scenario: Supplying 300 MHz LVDS and 100 MHz HCSL clocks to Xilinx Versal ACAP fabric and memory interfaces in real-time video analytics hardware.

IC Role / Device Role / Timing Role: Configurable buffer and level translator generating mixed-format clocks from a single 100 MHz differential input.

Use Value: Enables direct connection to both FPGA I/O banks and DDR4 memory controllers without external voltage translators or fanout buffers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B02427-GMR	Same silicon; differs only in factory-programmed configuration (different default output frequencies and I²C address)	Pre-configured for alternate reference-to-output mapping; requires no initial ClockBuilder Pro setup	Select when requiring out-of-box operation with specific preloaded timing profiles
LMK04832RHAT	Two PLLs + eight outputs; higher power (125 mA core); supports JESD204B subclass 1 deterministic latency	Targeted at RF/data converter timing; includes dual-loop jitter cleaning and digital delay calibration	Select when deterministic latency, ultra-low additive jitter (<50 fs), or JESD204B synchronization is required

Compared with Si5338A-B02427-GMR, the SI5338A-B02426-GMR offers identical electrical performance but distinct factory firmware; versus LMK04832RHAT, it trades lower power (45 mA vs. 125 mA) and smaller footprint (4×4 mm vs. 7×7 mm) for reduced jitter-cleaning capability and no JESD204B support.

Availability

SI5338A-B02426-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10 GbE switch clocking, and broadcast video sync applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B02426-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 family is designed for high-performance, multi-protocol serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where low jitter, flexible frequency synthesis, and compact integration are critical.

FAQ

What is the maximum output frequency supported by the SI5338A-B02426-GMR?

The SI5338A-B02426-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), as defined in the synthesis architecture.

Does the SI5338A-B02426-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338A-B02426-GMR is explicitly validated for PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical 0.11 ps) when configured with a PLL bandwidth of 2–4 MHz and CDR set to 10 MHz, meeting PCI-SIG Base Specification 4.0 requirements.

Can the SI5338A-B02426-GMR generate different output voltages on each of its four output banks?

Yes, the SI5338A-B02426-GMR provides independent VDDO0–VDDO3 supplies, allowing each output bank to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage FPGAs, ASICs, and memory subsystems without external level shifters.

How is the SI5338A-B02426-GMR programmed, and is external nonvolatile memory required?

The SI5338A-B02426-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. It contains on-chip OTP NVM, so no external memory is needed-configuration persists after power cycle once written to OTP.

What is the thermal resistance (θJA) of the SI5338A-B02426-GMR in its 24-pin QFN package?

The SI5338A-B02426-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions, measured in the standard 4-layer JEDEC PCB layout. Its exposed thermal pad must be soldered to a solid copper pour for optimal thermal performance.

SI5338A-B02426-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B02426-GMR FAQ

1.How can I place an order for SI5338A-B02426-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B02426-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B02426-GMR reliable?

The price and inventory of SI5338A-B02426-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B02426-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B02426-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B02426-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B02426-GMR?

SI5338A-B02426-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B02426-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B02426-GMR?

For technical support, including SI5338A-B02426-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B02426-GMR requirements.

6.How does Aetrix verify that SI5338A-B02426-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B02426-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B02426-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B02426-GMR?

All SI5338A-B02426-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B02426-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B02426-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B02426-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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