Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B04149-GM

Name: SI5338A-B04149-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B04149-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338A-B04149-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B04149-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,600

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338A-B04149-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ PLL architecture to synthesize independent frequencies up to 710 MHz on four differential outputs with 0 ppm frequency accuracy, 0.7 ps RMS phase jitter (typ), and PCIe Gen 1–4 Common Clock & Gen 3 SRNS compliance - deployed in high-speed serial interconnects such as PCIe switch cards and 10 GbE line interfaces.

For engineers reviewing the SI5338A-B04149-GM datasheet, SI5338A-B04149-GM pinout, SI5338A-B04149-GM application, or SI5338A-B04149-GM equivalent, key selection considerations include its 4× independent output voltage control (1.5/1.8/2.5/3.3 V), flexible input support (crystal, CMOS, SSTL/HSTL, differential), <20 ps phase step resolution, and spread-spectrum capability (0.5–5.0% deviation, 33–63 kHz modulation).

Technical Context

The SI5338A-B04149-GM integrates a two-stage synthesis architecture: a high-stability PLL (1.6 MHz loop bandwidth) locks to one of six inputs (IN1–IN6), followed by four independent MultiSynth™ fractional-N dividers enabling any-frequency synthesis per output. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable slew rate and termination.

It features dual-mode operation - full PLL-based synthesis for ultra-low jitter, or PLL-bypass buffer mode with additive phase jitter as low as 0.165 ps RMS (12 kHz–20 MHz) - and includes loss-of-lock/loss-of-signal alarms, independent frequency/phase increment/decrement controls, and zero-delay external feedback mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B through CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS
Frequency range per output	0.16–710 MHz (LVPECL/LVDS); 0.16–250 MHz (HCSL); 0.16–350 MHz (SSTL/HSTL); 0.16–200 MHz (CMOS)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and Gen 4 common clock specs
Input reference support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply voltages	Core: 1.8/2.5/3.3 V (±10%); Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom infrastructure use
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5338A-B04149-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled differential references up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); internal 20 kΩ pull-up/pull-down configurable
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each pair (e.g., CLK0A/CLK0B) delivers complementary signal with programmable format/voltage
VDDO0–VDDO3	Output buffer supplies	Independent power rails per output bank enable mixed-voltage system interfacing (e.g., 1.8 V FPGA + 3.3 V PHY)
VDD	Core supply	Single 1.8/2.5/3.3 V rail powers PLL, logic, and configuration memory; PSRR optimized for noise immunity
SCL, SDA	I²C interface	SMBus-compatible 2-wire bus (up to 400 kHz) for register programming and status readback
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock, loss-of-signal, or configuration error

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true zero-ppm frequency accuracy across all outputs without external crystals
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps step resolution enables precise timing alignment in multi-lane SerDes systems
Spread spectrum clocking (SSC)	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI in dense PCB layouts
Glitchless frequency tuning	Independent frequency increment/decrement via pins or I²C in 1 ppm steps, with update time ≤667 ns above 18 MHz
Flexible input multiplexing	6-input mux (2 differential pairs + 2 single-ended) with automatic failover and LOS detection supports redundant clock architectures
Low-power operation	45 mA typical core current at 100 MHz output; <12 mA in buffer-only mode - suitable for thermally constrained modules

Applications

PCIe Switch Card Timing	10 GbE Line Interface
Use Scenario: High-density server switch ASIC requiring synchronized 100 MHz reference clocks for multiple PCIe Gen 4 lanes and embedded SerDes blocks. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter 100 MHz HCSL outputs compliant with PCIe Gen 4 common clock spec (0.15–0.45 ps RMS jitter). Use Value: Eliminates need for four discrete oscillators; enables dynamic frequency margining and phase alignment across lanes via I²C.	Use Scenario: Optical transport module with SFP+ cages needing 156.25 MHz and 312.5 MHz clocks for MAC/PHY layers and gearbox logic. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating both frequencies simultaneously from a single 25 MHz crystal reference. Use Value: Reduces BOM count and layout area; supports protocol agility (1G/10G/25G) via field-upgradable configuration.
FPGA-Based Video Processing	Telecom Line Card Sync
Use Scenario: Broadcast video encoder using Xilinx Kintex Ultrascale+ FPGA with multiple clock domains (27 MHz SDI, 74.25 MHz HD-SDI, 148.5 MHz 3G-SDI). IC Role / Device Role / Timing Role: Programmable quad clock source delivering three precisely phase-aligned video clocks plus a 100 MHz system clock. Use Value: Achieves sub-20 ps inter-output skew; eliminates external delay lines and manual board-level tuning.	Use Scenario: Carrier-grade ONU/OLT line card requiring IEEE 1588 PTP grandmaster clock synchronization and SONET/OTN framing clocks. IC Role / Device Role / Timing Role: Dual-reference clock translator accepting 19.44 MHz OC-12 and 10 MHz GPS-disciplined inputs to generate 155.52 MHz, 622.08 MHz, and 2.488 GHz outputs. Use Value: Meets OC-12 random jitter spec (0.7 ps RMS); supports holdover during GPS outage via internal oscillator stability.

PCIe Switch Card Timing

10 GbE Line Interface

Use Scenario: High-density server switch ASIC requiring synchronized 100 MHz reference clocks for multiple PCIe Gen 4 lanes and embedded SerDes blocks.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter 100 MHz HCSL outputs compliant with PCIe Gen 4 common clock spec (0.15–0.45 ps RMS jitter).

Use Value: Eliminates need for four discrete oscillators; enables dynamic frequency margining and phase alignment across lanes via I²C.

Use Scenario: Optical transport module with SFP+ cages needing 156.25 MHz and 312.5 MHz clocks for MAC/PHY layers and gearbox logic.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating both frequencies simultaneously from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and layout area; supports protocol agility (1G/10G/25G) via field-upgradable configuration.

FPGA-Based Video Processing

Telecom Line Card Sync

Use Scenario: Broadcast video encoder using Xilinx Kintex Ultrascale+ FPGA with multiple clock domains (27 MHz SDI, 74.25 MHz HD-SDI, 148.5 MHz 3G-SDI).

IC Role / Device Role / Timing Role: Programmable quad clock source delivering three precisely phase-aligned video clocks plus a 100 MHz system clock.

Use Value: Achieves sub-20 ps inter-output skew; eliminates external delay lines and manual board-level tuning.

Use Scenario: Carrier-grade ONU/OLT line card requiring IEEE 1588 PTP grandmaster clock synchronization and SONET/OTN framing clocks.

IC Role / Device Role / Timing Role: Dual-reference clock translator accepting 19.44 MHz OC-12 and 10 MHz GPS-disciplined inputs to generate 155.52 MHz, 622.08 MHz, and 2.488 GHz outputs.

Use Value: Meets OC-12 random jitter spec (0.7 ps RMS); supports holdover during GPS outage via internal oscillator stability.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06189-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and multi-core processor clock trees - over-spec for basic PCIe/10GbE use	Choose when >4 outputs, tighter jitter, or deterministic latency are required; higher cost and larger 32-QFN package
ICS8430I-01T	Fixed-function 4-output LVDS generator; no I²C programming; max 350 MHz output; 1.2 ps RMS jitter	Limited to pre-defined frequency combinations; no spread spectrum or phase adjustment	Choose only for cost-sensitive, static-clock applications where flexibility is unnecessary and jitter budget allows ≥1.2 ps RMS

Compared with Si5332A-D06189-GM and ICS8430I-01T, the SI5338A-B04149-GM balances programmability, jitter performance, and footprint - offering full I²C configurability in a compact 24-QFN while meeting PCIe Gen 4 and 10 GbE timing requirements without over-engineering.

Availability

SI5338A-B04149-GM is available at Aetrix Electronics and suitable for PCIe switch cards, 10 GbE optical modules, broadcast video encoders, and telecom line cards requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B04149-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 family was designed as a highly configurable, low-jitter clock generator platform for high-speed serial data links - targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems where precision timing, multi-format output, and software-defined frequency agility are critical.

FAQ

What is the maximum output frequency supported by SI5338A-B04149-GM in LVPECL mode?

The SI5338A-B04149-GM supports up to 710 MHz on LVPECL outputs when operating in integer synthesis mode. For frequencies above 350 MHz, only two unique outputs may exceed that threshold simultaneously (Fvco/4 and Fvco/6), as specified in Skyworks Rev. 1.6 datasheet Table 6. This constraint ensures phase noise and jitter remain within specification across all active outputs.

Does SI5338A-B04149-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338A-B04149-GM meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines - including PLL bandwidth setting (2–4 MHz), CDR frequency (10 MHz), and HCSL 100 MHz output format. Validation is confirmed using the Skyworks PCIe Clock Jitter Tool.

Can SI5338A-B04149-GM generate different output voltages on each channel?

Yes, SI5338A-B04149-GM provides independent VDDO0–VDDO3 supply pins, allowing each of its four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices - for example, driving a 1.8 V FPGA bank and a 3.3 V PHY simultaneously without level shifters.

How is the SI5338A-B04149-GM programmed, and what tools are required?

SI5338A-B04149-GM is programmed via its I²C/SMBus interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. The tool generates custom configuration files (.cbs), validates timing constraints, and supports in-system programming - eliminating need for external programmers. Configuration is stored in on-chip OTP memory for power-on readiness.

What is the thermal performance of SI5338A-B04149-GM in a standard 4-layer PCB?

SI5338A-B04149-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. With proper PCB layout - including a 6 mm² thermal pad connected to ≥2 internal ground planes via ≥6 vias - it maintains safe junction temperature (<110 °C) at full load (45 mA core current) across –40 °C to +85 °C ambient, per Skyworks thermal characterization (Table 4).

SI5338A-B04149-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B04149-GM FAQ

1.How can I place an order for SI5338A-B04149-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B04149-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B04149-GM reliable?

The price and inventory of SI5338A-B04149-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B04149-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B04149-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B04149-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B04149-GM?

SI5338A-B04149-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B04149-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B04149-GM?

For technical support, including SI5338A-B04149-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B04149-GM requirements.

6.How does Aetrix verify that SI5338A-B04149-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B04149-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B04149-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B04149-GM?

All SI5338A-B04149-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B04149-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B04149-GM part is unused and in its original packaging.

Return procedure for SI5338A-B04149-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…